3059c2f5a8
The ast2500 uses the watchdog to reset the SDRAM controller. This operation is usually performed by u-boot's memory training procedure, and it is enabled by setting a bit in the SCU and then causing the watchdog to expire. Therefore, we need the watchdog to be able to access the SCU's register space. This causes the watchdog to not perform a system reset when the bit is set. In the future it could perform a reset of the SDMC model. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190621065242.32535-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37 lines
770 B
C
37 lines
770 B
C
/*
|
|
* ASPEED Watchdog Controller
|
|
*
|
|
* Copyright (C) 2016-2017 IBM Corp.
|
|
*
|
|
* This code is licensed under the GPL version 2 or later. See the
|
|
* COPYING file in the top-level directory.
|
|
*/
|
|
|
|
#ifndef WDT_ASPEED_H
|
|
#define WDT_ASPEED_H
|
|
|
|
#include "hw/sysbus.h"
|
|
|
|
#define TYPE_ASPEED_WDT "aspeed.wdt"
|
|
#define ASPEED_WDT(obj) \
|
|
OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
|
|
|
|
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
|
|
|
|
typedef struct AspeedWDTState {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
QEMUTimer *timer;
|
|
|
|
/*< public >*/
|
|
MemoryRegion iomem;
|
|
uint32_t regs[ASPEED_WDT_REGS_MAX];
|
|
|
|
AspeedSCUState *scu;
|
|
uint32_t pclk_freq;
|
|
uint32_t silicon_rev;
|
|
uint32_t ext_pulse_width_mask;
|
|
} AspeedWDTState;
|
|
|
|
#endif /* WDT_ASPEED_H */
|