qemu/target/riscv
Michael Clark b02403363f
RISC-V: Workaround for critical mstatus.FS bug
This change is a workaround for a bug where mstatus.FS
is not correctly reporting dirty after operations that
modify floating point registers. This a critical bug
or RISC-V in QEMU as it results in floating point
register file corruption when running SMP Linux due to
task migration and possibly uniprocessor Linux if
more than one process is using the FPU.

This workaround will return dirty if mstatus.FS is
switched from off to initial or clean. According to
the specification it is legal for an implementation
to return only off, or dirty.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-29 10:22:26 -07:00
..
cpu_bits.h
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
cpu.c RISC-V: Convert cpu definition to future model 2018-03-28 11:12:02 -07:00
cpu.h cpu: add CPU_RESOLVING_TYPE macro 2018-03-19 14:10:36 -03:00
fpu_helper.c RISC-V FPU Support 2018-03-07 08:30:28 +13:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.c
helper.h
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V: Workaround for critical mstatus.FS bug 2018-03-29 10:22:26 -07:00
pmp.c RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00