7f89fdf8eb
From https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms
When passing an argument with 16-byte alignment in integer registers,
Apple platforms allow the argument to start in an odd-numbered xN
register. The standard ABI requires it to begin in an even-numbered
xN register.
Cc: qemu-stable@nongnu.org
Fixes: 5427a9a760 ("tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2169
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <9fc0c2c7-dd57-459e-aecb-528edb74b4a7@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
176 lines
6.2 KiB
C
176 lines
6.2 KiB
C
/*
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* Initial TCG Implementation for aarch64
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*
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* Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
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* Written by Claudio Fontana
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or
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* (at your option) any later version.
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*
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* See the COPYING file in the top-level directory for details.
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*/
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#ifndef AARCH64_TCG_TARGET_H
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#define AARCH64_TCG_TARGET_H
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#include "host/cpuinfo.h"
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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typedef enum {
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TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
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TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
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TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
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TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
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TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
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TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
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TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
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TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
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/* X31 is either the stack pointer or zero, depending on context. */
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TCG_REG_SP = 31,
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TCG_REG_XZR = 31,
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TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
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TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
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TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
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TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
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TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
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TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
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TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
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TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
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/* Aliases. */
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TCG_REG_FP = TCG_REG_X29,
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TCG_REG_LR = TCG_REG_X30,
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TCG_AREG0 = TCG_REG_X19,
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} TCGReg;
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#define TCG_TARGET_NB_REGS 64
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_SP
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
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#ifdef CONFIG_DARWIN
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
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#else
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
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#endif
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#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
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#define have_lse (cpuinfo & CPUINFO_LSE)
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#define have_lse2 (cpuinfo & CPUINFO_LSE2)
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 1
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_extr_i64_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 1
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_clz_i64 1
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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/*
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* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
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* which requires writable pages. We must defer to the helper for user-only,
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* but in system mode all ram is writable for the host.
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*/
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#ifdef CONFIG_USER_ONLY
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#define TCG_TARGET_HAS_qemu_ldst_i128 have_lse2
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#else
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#define TCG_TARGET_HAS_qemu_ldst_i128 1
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#endif
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#define TCG_TARGET_HAS_tst 1
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#define TCG_TARGET_HAS_v64 1
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#define TCG_TARGET_HAS_v128 1
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#define TCG_TARGET_HAS_v256 0
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec 1
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#define TCG_TARGET_HAS_nand_vec 0
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#define TCG_TARGET_HAS_nor_vec 0
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#define TCG_TARGET_HAS_eqv_vec 0
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 1
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#define TCG_TARGET_HAS_abs_vec 1
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#define TCG_TARGET_HAS_roti_vec 0
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#define TCG_TARGET_HAS_rots_vec 0
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#define TCG_TARGET_HAS_rotv_vec 0
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif /* AARCH64_TCG_TARGET_H */
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