358 lines
10 KiB
C
358 lines
10 KiB
C
/*
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* QEMU IDE Emulation: PCI cmd646 support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/i386/pc.h>
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#include <hw/pci/pci.h>
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#include <hw/isa/isa.h>
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#include "block/block.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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#include <hw/ide/pci.h>
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/* CMD646 specific */
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#define MRDMODE 0x71
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#define MRDMODE_INTR_CH0 0x04
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#define MRDMODE_INTR_CH1 0x08
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#define MRDMODE_BLK_CH0 0x10
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#define MRDMODE_BLK_CH1 0x20
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#define UDIDETCR0 0x73
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#define UDIDETCR1 0x7B
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static void cmd646_update_irq(PCIIDEState *d);
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static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (addr != 2 || size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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return ide_status_read(cmd646bar->bus, addr + 2);
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}
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static void cmd646_cmd_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (addr != 2 || size != 1) {
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return;
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}
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ide_cmd_write(cmd646bar->bus, addr + 2, data);
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}
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static const MemoryRegionOps cmd646_cmd_ops = {
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.read = cmd646_cmd_read,
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.write = cmd646_cmd_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (size == 1) {
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return ide_ioport_read(cmd646bar->bus, addr);
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} else if (addr == 0) {
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if (size == 2) {
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return ide_data_readw(cmd646bar->bus, addr);
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} else {
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return ide_data_readl(cmd646bar->bus, addr);
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}
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}
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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static void cmd646_data_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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CMD646BAR *cmd646bar = opaque;
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if (size == 1) {
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ide_ioport_write(cmd646bar->bus, addr, data);
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} else if (addr == 0) {
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if (size == 2) {
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ide_data_writew(cmd646bar->bus, addr, data);
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} else {
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ide_data_writel(cmd646bar->bus, addr, data);
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}
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}
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}
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static const MemoryRegionOps cmd646_data_ops = {
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.read = cmd646_data_read,
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.write = cmd646_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
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{
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IDEBus *bus = &d->bus[bus_num];
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CMD646BAR *bar = &d->cmd646_bar[bus_num];
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bar->bus = bus;
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bar->pci_dev = d;
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memory_region_init_io(&bar->cmd, NULL, &cmd646_cmd_ops, bar, "cmd646-cmd", 4);
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memory_region_init_io(&bar->data, NULL, &cmd646_data_ops, bar, "cmd646-data", 8);
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}
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static uint64_t bmdma_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev = bm->pci_dev;
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch(addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 1:
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val = pci_dev->dev.config[MRDMODE];
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break;
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case 2:
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val = bm->status;
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break;
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case 3:
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if (bm == &pci_dev->bmdma[0]) {
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val = pci_dev->dev.config[UDIDETCR0];
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} else {
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val = pci_dev->dev.config[UDIDETCR1];
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}
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BMDMAState *bm = opaque;
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PCIIDEState *pci_dev = bm->pci_dev;
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if (size != 1) {
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return;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
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#endif
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switch(addr & 3) {
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case 0:
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bmdma_cmd_writeb(bm, val);
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break;
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case 1:
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pci_dev->dev.config[MRDMODE] =
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(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
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cmd646_update_irq(pci_dev);
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break;
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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case 3:
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if (bm == &pci_dev->bmdma[0])
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pci_dev->dev.config[UDIDETCR0] = val;
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else
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pci_dev->dev.config[UDIDETCR1] = val;
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break;
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}
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}
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static const MemoryRegionOps cmd646_bmdma_ops = {
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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{
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BMDMAState *bm;
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int i;
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memory_region_init(&d->bmdma_bar, NULL, "cmd646-bmdma", 16);
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for(i = 0;i < 2; i++) {
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bm = &d->bmdma[i];
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memory_region_init_io(&bm->extra_io, NULL, &cmd646_bmdma_ops, bm,
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"cmd646-bmdma-bus", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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memory_region_init_io(&bm->addr_ioport, NULL, &bmdma_addr_ioport_ops, bm,
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"cmd646-bmdma-ioport", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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}
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}
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/* XXX: call it also when the MRDMODE is changed from the PCI config
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registers */
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static void cmd646_update_irq(PCIIDEState *d)
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{
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int pci_level;
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pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
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((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
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!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
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qemu_set_irq(d->dev.irq[0], pci_level);
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}
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/* the PCI irq level is the logical OR of the two channels */
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static void cmd646_set_irq(void *opaque, int channel, int level)
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{
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PCIIDEState *d = opaque;
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int irq_mask;
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irq_mask = MRDMODE_INTR_CH0 << channel;
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if (level)
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d->dev.config[MRDMODE] |= irq_mask;
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else
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d->dev.config[MRDMODE] &= ~irq_mask;
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cmd646_update_irq(d);
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}
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static void cmd646_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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unsigned int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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}
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/* CMD646 PCI IDE controller */
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static int pci_cmd646_ide_initfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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uint8_t *pci_conf = d->dev.config;
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qemu_irq *irq;
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int i;
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pci_conf[PCI_CLASS_PROG] = 0x8f;
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pci_conf[0x51] = 0x04; // enable IDE0
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if (d->secondary) {
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/* XXX: if not enabled, really disable the seconday IDE controller */
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pci_conf[0x51] |= 0x08; /* enable IDE1 */
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}
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setup_cmd646_bar(d, 0);
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setup_cmd646_bar(d, 1);
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
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pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
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pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
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pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
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bmdma_setup_bar(d);
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pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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/* TODO: RST# value should be 0 */
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pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
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irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
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for (i = 0; i < 2; i++) {
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ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
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ide_init2(&d->bus[i], irq[i]);
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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d->bmdma[i].bus = &d->bus[i];
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qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
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&d->bmdma[i].dma);
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}
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vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
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qemu_register_reset(cmd646_reset, d);
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return 0;
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}
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static void pci_cmd646_ide_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_destroy(&d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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memory_region_destroy(&d->bmdma[i].addr_ioport);
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memory_region_destroy(&d->cmd646_bar[i].cmd);
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memory_region_destroy(&d->cmd646_bar[i].data);
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}
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memory_region_destroy(&d->bmdma_bar);
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}
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void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
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int secondary_ide_enabled)
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{
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PCIDevice *dev;
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dev = pci_create(bus, -1, "cmd646-ide");
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qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
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qdev_init_nofail(&dev->qdev);
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pci_ide_create_devs(dev, hd_table);
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}
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static Property cmd646_ide_properties[] = {
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DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cmd646_ide_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = pci_cmd646_ide_initfn;
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k->exit = pci_cmd646_ide_exitfn;
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k->vendor_id = PCI_VENDOR_ID_CMD;
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k->device_id = PCI_DEVICE_ID_CMD_646;
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k->revision = 0x07;
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k->class_id = PCI_CLASS_STORAGE_IDE;
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dc->props = cmd646_ide_properties;
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}
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static const TypeInfo cmd646_ide_info = {
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.name = "cmd646-ide",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIIDEState),
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.class_init = cmd646_ide_class_init,
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};
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static void cmd646_ide_register_types(void)
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{
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type_register_static(&cmd646_ide_info);
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}
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type_init(cmd646_ide_register_types)
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