d49805aeea
After previous Peter patch, they are redundant. This way we don't
assign them except when needed. Once there, there were lots of case
where the ".fields" indentation was wrong:
.fields = (VMStateField []) {
and
.fields = (VMStateField []) {
Change all the combinations to:
.fields = (VMStateField[]){
The biggest problem (appart from aesthetics) was that checkpatch complained
when we copy&pasted the code from one place to another.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Acked-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
575 lines
17 KiB
C
575 lines
17 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/isa/apm.h"
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#include "hw/i2c/pm_smbus.h"
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#include "hw/pci/pci.h"
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#include "hw/acpi/acpi.h"
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#include "sysemu/sysemu.h"
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#include "qemu/range.h"
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#include "exec/ioport.h"
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#include "hw/nvram/fw_cfg.h"
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#include "exec/address-spaces.h"
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#include "hw/acpi/piix4.h"
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#include "hw/acpi/pcihp.h"
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#include "hw/acpi/cpu_hotplug.h"
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#include "hw/hotplug.h"
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0)
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#endif
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#define GPE_BASE 0xafe0
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#define GPE_LEN 4
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struct pci_status {
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uint32_t up; /* deprecated, maintained for migration compatibility */
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uint32_t down;
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};
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typedef struct PIIX4PMState {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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MemoryRegion io;
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uint32_t io_base;
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MemoryRegion io_gpe;
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ACPIREGS ar;
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APMState apm;
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PMSMBus smb;
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uint32_t smb_io_base;
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qemu_irq irq;
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qemu_irq smi_irq;
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int kvm_enabled;
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Notifier machine_ready;
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Notifier powerdown_notifier;
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AcpiPciHpState acpi_pci_hotplug;
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bool use_acpi_pci_hotplug;
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uint8_t disable_s3;
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uint8_t disable_s4;
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uint8_t s4_val;
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AcpiCpuHotplug gpe_cpu;
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Notifier cpu_added_notifier;
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} PIIX4PMState;
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#define TYPE_PIIX4_PM "PIIX4_PM"
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#define PIIX4_PM(obj) \
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OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
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static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
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PCIBus *bus, PIIX4PMState *s);
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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static void pm_tmr_timer(ACPIREGS *ar)
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{
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PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
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acpi_update_sci(&s->ar, s->irq);
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}
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static void apm_ctrl_changed(uint32_t val, void *arg)
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{
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PIIX4PMState *s = arg;
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PCIDevice *d = PCI_DEVICE(s);
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/* ACPI specs 3.0, 4.7.2.5 */
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acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
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if (d->config[0x5b] & (1 << 1)) {
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq);
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}
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}
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}
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static void pm_io_space_update(PIIX4PMState *s)
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{
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PCIDevice *d = PCI_DEVICE(s);
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s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
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s->io_base &= 0xffc0;
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memory_region_transaction_begin();
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memory_region_set_enabled(&s->io, d->config[0x80] & 1);
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memory_region_set_address(&s->io, s->io_base);
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memory_region_transaction_commit();
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}
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static void smbus_io_space_update(PIIX4PMState *s)
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{
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PCIDevice *d = PCI_DEVICE(s);
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s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
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s->smb_io_base &= 0xffc0;
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memory_region_transaction_begin();
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memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
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memory_region_set_address(&s->smb.io, s->smb_io_base);
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memory_region_transaction_commit();
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(d, address, val, len);
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if (range_covers_byte(address, len, 0x80) ||
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ranges_overlap(address, len, 0x40, 4)) {
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pm_io_space_update((PIIX4PMState *)d);
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}
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if (range_covers_byte(address, len, 0xd2) ||
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ranges_overlap(address, len, 0x90, 4)) {
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smbus_io_space_update((PIIX4PMState *)d);
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}
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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pm_io_space_update(s);
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return 0;
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}
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \
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.name = (stringify(_field)), \
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.version_id = 0, \
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.info = &vmstate_info_uint16, \
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.size = sizeof(uint16_t), \
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.flags = VMS_SINGLE | VMS_POINTER, \
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
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}
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static const VMStateDescription vmstate_gpe = {
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.name = "gpe",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_GPE_ARRAY(sts, ACPIGPE),
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VMSTATE_GPE_ARRAY(en, ACPIGPE),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pci_status = {
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.name = "pci_status",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
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VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
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VMSTATE_END_OF_LIST()
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}
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};
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static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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int ret, i;
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uint16_t temp;
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ret = pci_device_load(PCI_DEVICE(s), f);
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if (ret < 0) {
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return ret;
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}
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qemu_get_be16s(f, &s->ar.pm1.evt.sts);
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qemu_get_be16s(f, &s->ar.pm1.evt.en);
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qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
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ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
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if (ret) {
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return ret;
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}
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timer_get(f, s->ar.tmr.timer);
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qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
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qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
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for (i = 0; i < 3; i++) {
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qemu_get_be16s(f, &temp);
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}
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qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
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for (i = 0; i < 3; i++) {
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qemu_get_be16s(f, &temp);
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}
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ret = vmstate_load_state(f, &vmstate_pci_status,
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&s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
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return ret;
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}
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static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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return s->use_acpi_pci_hotplug;
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}
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static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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return !s->use_acpi_pci_hotplug;
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}
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/* qemu-kvm 1.2 uses version 3 but advertised as 2
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* To support incoming qemu-kvm 1.2 migration, change version_id
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* and minimum_version_id to 2 below (which breaks migration from
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* qemu 1.2).
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*
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*/
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static const VMStateDescription vmstate_acpi = {
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.name = "piix4_pm",
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 1,
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.load_state_old = acpi_load_old,
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.post_load = vmstate_acpi_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
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VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
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VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
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VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
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VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
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VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
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VMSTATE_STRUCT_TEST(
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acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
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PIIX4PMState,
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vmstate_test_no_use_acpi_pci_hotplug,
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2, vmstate_pci_status,
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struct AcpiPciHpPciStatus),
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VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
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vmstate_test_use_acpi_pci_hotplug),
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VMSTATE_END_OF_LIST()
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}
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};
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static void piix4_reset(void *opaque)
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{
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PIIX4PMState *s = opaque;
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PCIDevice *d = PCI_DEVICE(s);
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uint8_t *pci_conf = d->config;
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pci_conf[0x58] = 0;
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pci_conf[0x59] = 0;
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pci_conf[0x5a] = 0;
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pci_conf[0x5b] = 0;
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pci_conf[0x40] = 0x01; /* PM io base read only bit */
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pci_conf[0x80] = 0;
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02;
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}
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pm_io_space_update(s);
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acpi_pcihp_reset(&s->acpi_pci_hotplug);
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}
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static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
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{
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PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
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assert(s != NULL);
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acpi_pm1_evt_power_down(&s->ar);
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}
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static void piix4_pci_device_plug_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp)
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{
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PIIX4PMState *s = PIIX4_PM(hotplug_dev);
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acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, errp);
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}
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static void piix4_pci_device_unplug_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp)
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{
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PIIX4PMState *s = PIIX4_PM(hotplug_dev);
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acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
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errp);
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}
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static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
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{
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PIIX4PMState *s = opaque;
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qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
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}
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static void piix4_pm_machine_ready(Notifier *n, void *opaque)
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{
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PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
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PCIDevice *d = PCI_DEVICE(s);
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MemoryRegion *io_as = pci_address_space_io(d);
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uint8_t *pci_conf;
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pci_conf = d->config;
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pci_conf[0x5f] = 0x10 |
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(memory_region_present(io_as, 0x378) ? 0x80 : 0);
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pci_conf[0x63] = 0x60;
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pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
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(memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
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if (s->use_acpi_pci_hotplug) {
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pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
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} else {
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piix4_update_bus_hotplug(d->bus, s);
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}
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}
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static void piix4_pm_add_propeties(PIIX4PMState *s)
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{
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static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
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static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
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static const uint32_t gpe0_blk = GPE_BASE;
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static const uint32_t gpe0_blk_len = GPE_LEN;
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static const uint16_t sci_int = 9;
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object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
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&acpi_enable_cmd, NULL);
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object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
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&acpi_disable_cmd, NULL);
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object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
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&gpe0_blk, NULL);
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object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
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&gpe0_blk_len, NULL);
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object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
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&sci_int, NULL);
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object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
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&s->io_base, NULL);
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}
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static int piix4_pm_initfn(PCIDevice *dev)
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{
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PIIX4PMState *s = PIIX4_PM(dev);
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uint8_t *pci_conf;
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pci_conf = dev->config;
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pci_conf[0x06] = 0x80;
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pci_conf[0x07] = 0x02;
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pci_conf[0x09] = 0x00;
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pci_conf[0x3d] = 0x01; // interrupt pin 1
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/* APM */
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apm_init(dev, &s->apm, apm_ctrl_changed, s);
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if (s->kvm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pci_conf[0x5B] = 0x02;
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}
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/* XXX: which specification is used ? The i82731AB has different
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mappings */
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pci_conf[0x90] = s->smb_io_base | 1;
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pci_conf[0x91] = s->smb_io_base >> 8;
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pci_conf[0xd2] = 0x09;
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pm_smbus_init(DEVICE(dev), &s->smb);
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memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
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memory_region_add_subregion(pci_address_space_io(dev),
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s->smb_io_base, &s->smb.io);
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memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
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memory_region_set_enabled(&s->io, false);
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memory_region_add_subregion(pci_address_space_io(dev),
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0, &s->io);
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acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val);
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acpi_gpe_init(&s->ar, GPE_LEN);
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s->powerdown_notifier.notify = piix4_pm_powerdown_req;
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qemu_register_powerdown_notifier(&s->powerdown_notifier);
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s->machine_ready.notify = piix4_pm_machine_ready;
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qemu_add_machine_init_done_notifier(&s->machine_ready);
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qemu_register_reset(piix4_reset, s);
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piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
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piix4_pm_add_propeties(s);
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return 0;
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}
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Object *piix4_pm_find(void)
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{
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bool ambig;
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Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
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if (ambig || !o) {
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return NULL;
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}
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return o;
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}
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I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq smi_irq,
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int kvm_enabled, FWCfgState *fw_cfg)
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{
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DeviceState *dev;
|
|
PIIX4PMState *s;
|
|
|
|
dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
|
|
qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
|
|
|
|
s = PIIX4_PM(dev);
|
|
s->irq = sci_irq;
|
|
s->smi_irq = smi_irq;
|
|
s->kvm_enabled = kvm_enabled;
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
if (fw_cfg) {
|
|
uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
|
|
suspend[3] = 1 | ((!s->disable_s3) << 7);
|
|
suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
|
|
|
|
fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
|
|
}
|
|
|
|
return s->smb.smbus;
|
|
}
|
|
|
|
static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
|
|
{
|
|
PIIX4PMState *s = opaque;
|
|
uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
|
|
|
|
PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
|
|
return val;
|
|
}
|
|
|
|
static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
|
|
unsigned width)
|
|
{
|
|
PIIX4PMState *s = opaque;
|
|
|
|
acpi_gpe_ioport_writeb(&s->ar, addr, val);
|
|
acpi_update_sci(&s->ar, s->irq);
|
|
|
|
PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
|
|
}
|
|
|
|
static const MemoryRegionOps piix4_gpe_ops = {
|
|
.read = gpe_readb,
|
|
.write = gpe_writeb,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.impl.min_access_size = 1,
|
|
.impl.max_access_size = 1,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static void piix4_cpu_added_req(Notifier *n, void *opaque)
|
|
{
|
|
PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier);
|
|
|
|
assert(s != NULL);
|
|
AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque));
|
|
acpi_update_sci(&s->ar, s->irq);
|
|
}
|
|
|
|
static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
|
|
PCIBus *bus, PIIX4PMState *s)
|
|
{
|
|
memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
|
|
"acpi-gpe0", GPE_LEN);
|
|
memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
|
|
|
|
acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
|
|
s->use_acpi_pci_hotplug);
|
|
|
|
AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu,
|
|
PIIX4_CPU_HOTPLUG_IO_BASE);
|
|
s->cpu_added_notifier.notify = piix4_cpu_added_req;
|
|
qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
|
|
}
|
|
|
|
static Property piix4_pm_properties[] = {
|
|
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
|
|
DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
|
|
DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
|
|
DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
|
|
DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
|
|
use_acpi_pci_hotplug, true),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void piix4_pm_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
|
|
|
|
k->init = piix4_pm_initfn;
|
|
k->config_write = pm_write_config;
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
|
|
k->revision = 0x03;
|
|
k->class_id = PCI_CLASS_BRIDGE_OTHER;
|
|
dc->desc = "PM";
|
|
dc->vmsd = &vmstate_acpi;
|
|
dc->props = piix4_pm_properties;
|
|
/*
|
|
* Reason: part of PIIX4 southbridge, needs to be wired up,
|
|
* e.g. by mips_malta_init()
|
|
*/
|
|
dc->cannot_instantiate_with_device_add_yet = true;
|
|
dc->hotpluggable = false;
|
|
hc->plug = piix4_pci_device_plug_cb;
|
|
hc->unplug = piix4_pci_device_unplug_cb;
|
|
}
|
|
|
|
static const TypeInfo piix4_pm_info = {
|
|
.name = TYPE_PIIX4_PM,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PIIX4PMState),
|
|
.class_init = piix4_pm_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_HOTPLUG_HANDLER },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void piix4_pm_register_types(void)
|
|
{
|
|
type_register_static(&piix4_pm_info);
|
|
}
|
|
|
|
type_init(piix4_pm_register_types)
|