Richard Henderson 2f668fabbc target/riscv: Avoid tcg_const_* ... All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2023-03-05 13:46:13 -08:00
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trans_privileged.c.inc	target/riscv: Add itrigger support when icount is not enabled	2023-01-06 10:42:55 +10:00
trans_rva.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvd.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvf.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvh.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_rvi.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvm.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvv.c.inc	target/riscv: Avoid tcg_const_*	2023-03-05 13:46:13 -08:00
trans_rvzawrs.c.inc	RISC-V: Add Zawrs ISA extension support	2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc	target/riscv: Avoid tcg_const_*	2023-03-05 13:46:13 -08:00
trans_rvzicond.c.inc	target/riscv: Add support for Zicond extension	2023-03-01 17:07:59 -08:00
trans_svinval.c.inc	target/riscv: Ensure opcode is saved for all relevant instructions	2023-02-07 08:19:23 +10:00
trans_xthead.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00