qemu/tests/tcg/mips/mips32-dsp/extr_w.c
Petar Jovanovic 8b758d0568 target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
Fix for rndrashift_short_acc to set correct value to higher 64 bits.
This change also corrects conditions when bit 23 of the DSPControl register
is set.

The existing test files have been extended with several examples that
trigger the issues. One bug/example in the test file for EXTR_RS_W has been
found and reported by Klaus Peichl.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-17 01:06:34 +01:00

95 lines
1.8 KiB
C

#include<stdio.h>
#include<assert.h>
int main()
{
int rt, ach, acl, dsp;
int result;
ach = 0x05;
acl = 0xB4CB;
result = 0xA0001699;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extr.w %0, $ac1, 0x03\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 23) & 0x01;
assert(dsp == 1);
assert(result == rt);
/* Clear dspcontrol */
dsp = 0;
__asm
("wrdsp %0\n\t"
:
: "r"(dsp)
);
ach = 0x01;
acl = 0xB4CB;
result = 0x10000B4C;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extr.w %0, $ac1, 0x04\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 23) & 0x01;
assert(dsp == 0);
assert(result == rt);
/* Clear dspcontrol */
dsp = 0;
__asm
("wrdsp %0\n\t"
:
: "r"(dsp)
);
ach = 0x3fffffff;
acl = 0x2bcdef01;
result = 0x7ffffffe;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extr.w %0, $ac1, 0x1F\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 23) & 0x01;
assert(dsp == 0);
assert(result == rt);
/* Clear dspcontrol */
dsp = 0;
__asm
("wrdsp %0\n\t"
:
: "r"(dsp)
);
ach = 0xFFFFFFFF;
acl = 0xFFFFFFFF;
result = 0xFFFFFFFF;
__asm
("mthi %2, $ac1\n\t"
"mtlo %3, $ac1\n\t"
"extr.w %0, $ac1, 0x1F\n\t"
"rddsp %1\n\t"
: "=r"(rt), "=r"(dsp)
: "r"(ach), "r"(acl)
);
dsp = (dsp >> 23) & 0x01;
assert(dsp == 0);
assert(result == rt);
return 0;
}