3e96b20528
Convert the Neon 2-reg-misc insns which are implemented with simple calls to functions that take the input, output and fpstatus pointer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-16-peter.maydell@linaro.org
386 lines
15 KiB
C
386 lines
15 KiB
C
#ifndef TARGET_ARM_TRANSLATE_H
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#define TARGET_ARM_TRANSLATE_H
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#include "exec/translator.h"
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#include "internals.h"
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/* internal defines */
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typedef struct DisasContext {
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DisasContextBase base;
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const ARMISARegisters *isar;
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/* The address of the current instruction being translated. */
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target_ulong pc_curr;
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target_ulong page_start;
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uint32_t insn;
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/* Nonzero if this instruction has been conditionally skipped. */
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int condjmp;
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/* The label that will be jumped to when the instruction is skipped. */
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TCGLabel *condlabel;
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/* Thumb-2 conditional execution bits. */
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int condexec_mask;
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int condexec_cond;
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int thumb;
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int sctlr_b;
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MemOp be_data;
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
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uint8_t tbii; /* TBI1|TBI0 for insns */
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uint8_t tbid; /* TBI1|TBI0 for data */
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bool ns; /* Use non-secure CPREG bank on access */
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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int sve_excp_el; /* SVE exception EL or 0 if enabled */
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int sve_len; /* SVE vector length in bytes */
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/* Flag indicating that exceptions from secure mode are routed to EL3. */
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bool secure_routed_to_el3;
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bool vfp_enabled; /* FP enabled via FPSCR.EN */
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int vec_len;
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int vec_stride;
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bool v7m_handler_mode;
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bool v8m_secure; /* true if v8M and we're in Secure mode */
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bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
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bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
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bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
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bool v7m_lspact; /* FPCCR.LSPACT set */
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/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
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* so that top level loop can generate correct syndrome information.
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*/
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uint32_t svc_imm;
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int aarch64;
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int current_el;
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/* Debug target exception level for single-step exceptions */
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int debug_target_el;
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GHashTable *cp_regs;
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uint64_t features; /* CPU features bits */
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/* Because unallocated encodings generate different exception syndrome
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* information from traps due to FP being disabled, we can't do a single
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* "is fp access disabled" check at a high level in the decode tree.
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* To help in catching bugs where the access check was forgotten in some
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* code path, we set this flag when the access check is done, and assert
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* that it is set at the point where we actually touch the FP regs.
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*/
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bool fp_access_checked;
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/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
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* single-step support).
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*/
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bool ss_active;
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bool pstate_ss;
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/* True if the insn just emitted was a load-exclusive instruction
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* (necessary for syndrome information for single step exceptions),
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* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
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*/
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bool is_ldex;
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/* True if AccType_UNPRIV should be used for LDTR et al */
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bool unpriv;
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/* True if v8.3-PAuth is active. */
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bool pauth_active;
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/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
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bool bt;
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/* True if any CP15 access is trapped by HSTR_EL2 */
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bool hstr_active;
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/*
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* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
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* < 0, set by the current instruction.
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*/
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int8_t btype;
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/* True if this page is guarded. */
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bool guarded_page;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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/* TCG op of the current insn_start. */
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TCGOp *insn_start;
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#define TMP_A64_MAX 16
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int tmp_a64_count;
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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} DisasContext;
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typedef struct DisasCompare {
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TCGCond cond;
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TCGv_i32 value;
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bool value_global;
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} DisasCompare;
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/* Share the TCG temporaries common between 32 and 64 bit modes. */
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extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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extern TCGv_i64 cpu_exclusive_addr;
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extern TCGv_i64 cpu_exclusive_val;
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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return (dc->features & (1ULL << feature)) != 0;
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}
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static inline int get_mem_index(DisasContext *s)
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{
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return arm_to_core_mmu_idx(s->mmu_idx);
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}
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/* Function used to determine the target exception EL when otherwise not known
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* or default.
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*/
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static inline int default_exception_el(DisasContext *s)
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{
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/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
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* there is no secure EL1, so we route exceptions to EL3. Otherwise,
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* exceptions can only be routed to ELs above 1, so we target the higher of
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* 1 or the current EL.
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*/
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return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
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? 3 : MAX(1, s->current_el);
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}
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static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
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{
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/* We don't need to save all of the syndrome so we mask and shift
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* out unneeded bits to help the sleb128 encoder do a better job.
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*/
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syn &= ARM_INSN_START_WORD2_MASK;
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syn >>= ARM_INSN_START_WORD2_SHIFT;
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/* We check and clear insn_start_idx to catch multiple updates. */
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assert(s->insn_start != NULL);
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tcg_set_insn_start_param(s->insn_start, 2, syn);
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s->insn_start = NULL;
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}
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/* is_jmp field values */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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#define DISAS_WFI DISAS_TARGET_2
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#define DISAS_SWI DISAS_TARGET_3
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/* WFE */
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#define DISAS_WFE DISAS_TARGET_4
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#define DISAS_HVC DISAS_TARGET_5
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#define DISAS_SMC DISAS_TARGET_6
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#define DISAS_YIELD DISAS_TARGET_7
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/* M profile branch which might be an exception return (and so needs
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* custom end-of-TB code)
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*/
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#define DISAS_BX_EXCRET DISAS_TARGET_8
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/* For instructions which want an immediate exit to the main loop,
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* as opposed to attempting to use lookup_and_goto_ptr. Unlike
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* DISAS_UPDATE this doesn't write the PC on exiting the translation
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* loop so you need to ensure something (gen_a64_set_pc_im or runtime
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* helper) has done so before we reach return from cpu_tb_exec.
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*/
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#define DISAS_EXIT DISAS_TARGET_9
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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void gen_a64_set_pc_im(uint64_t val);
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extern const TranslatorOps aarch64_translator_ops;
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#else
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static inline void a64_translate_init(void)
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{
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}
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static inline void gen_a64_set_pc_im(uint64_t val)
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{
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}
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#endif
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void arm_test_cc(DisasCompare *cmp, int cc);
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void arm_free_cc(DisasCompare *cmp);
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void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
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void arm_gen_test_cc(int cc, TCGLabel *label);
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/* Return state of Alternate Half-precision flag, caller frees result */
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static inline TCGv_i32 get_ahp_flag(void)
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{
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TCGv_i32 ret = tcg_temp_new_i32();
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tcg_gen_ld_i32(ret, cpu_env,
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offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
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tcg_gen_extract_i32(ret, ret, 26, 1);
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return ret;
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}
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/* Set bits within PSTATE. */
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static inline void set_pstate_bits(uint32_t bits)
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{
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TCGv_i32 p = tcg_temp_new_i32();
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tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
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tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_gen_ori_i32(p, p, bits);
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tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_temp_free_i32(p);
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}
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/* Clear bits within PSTATE. */
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static inline void clear_pstate_bits(uint32_t bits)
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{
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TCGv_i32 p = tcg_temp_new_i32();
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tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
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tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_gen_andi_i32(p, p, ~bits);
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tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_temp_free_i32(p);
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}
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/* If the singlestep state is Active-not-pending, advance to Active-pending. */
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static inline void gen_ss_advance(DisasContext *s)
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{
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if (s->ss_active) {
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s->pstate_ss = 0;
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clear_pstate_bits(PSTATE_SS);
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}
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}
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static inline void gen_exception(int excp, uint32_t syndrome,
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uint32_t target_el)
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{
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TCGv_i32 tcg_excp = tcg_const_i32(excp);
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TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
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TCGv_i32 tcg_el = tcg_const_i32(target_el);
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gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
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tcg_syn, tcg_el);
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tcg_temp_free_i32(tcg_el);
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tcg_temp_free_i32(tcg_syn);
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tcg_temp_free_i32(tcg_excp);
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}
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/* Generate an architectural singlestep exception */
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static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
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{
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bool same_el = (s->debug_target_el == s->current_el);
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/*
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* If singlestep is targeting a lower EL than the current one,
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* then s->ss_active must be false and we can never get here.
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*/
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assert(s->debug_target_el >= s->current_el);
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gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
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}
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/*
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* Given a VFP floating point constant encoded into an 8 bit immediate in an
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* instruction, expand it to the actual constant value of the specified
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* size, as per the VFPExpandImm() pseudocode in the Arm ARM.
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*/
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uint64_t vfp_expand_imm(int size, uint8_t imm8);
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/* Vector operations shared between ARM and AArch64. */
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void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
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void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
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void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
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void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
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void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
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void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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/*
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* Forward to the isar_feature_* tests given a DisasContext pointer.
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*/
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#define dc_isar_feature(name, ctx) \
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({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
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/* Note that the gvec expanders operate on offsets + sizes. */
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typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
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typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
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uint32_t, uint32_t);
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typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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/* Function prototype for gen_ functions for calling Neon helpers */
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typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
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typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
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typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
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typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
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typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
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typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
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typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
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typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
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typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
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typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
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typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
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typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
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typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
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typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
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typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
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typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
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typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
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#endif /* TARGET_ARM_TRANSLATE_H */
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