0bf4d77e59
The SBE (Self Boot Engine) are on-chip microcontrollers that perform early boot steps, as well as provide some runtime facilities (e.g., timer, secure register access, MPIPL). The latter facilities are accessed mostly via a message system called SBEFIFO. This driver provides initial emulation for the SBE runtime registers and a very basic SBEFIFO implementation that provides the timer command. This covers the basic SBE behaviour expected by skiboot when booting. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220811093726.1442343-1-npiggin@gmail.com> [danielhb: fixed SBE_HOST_RESPONSE_MASK long line] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/*
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* QEMU PowerPC PowerNV Emulation of some SBE behaviour
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*
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* Copyright (c) 2022, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_SBE_H
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#define PPC_PNV_SBE_H
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#include "qom/object.h"
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#define TYPE_PNV_SBE "pnv-sbe"
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OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)
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#define TYPE_PNV9_SBE TYPE_PNV_SBE "-POWER9"
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DECLARE_INSTANCE_CHECKER(PnvSBE, PNV9_SBE, TYPE_PNV9_SBE)
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#define TYPE_PNV10_SBE TYPE_PNV_SBE "-POWER10"
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DECLARE_INSTANCE_CHECKER(PnvSBE, PNV10_SBE, TYPE_PNV10_SBE)
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struct PnvSBE {
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DeviceState xd;
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uint64_t mbox[8];
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uint64_t sbe_doorbell;
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uint64_t host_doorbell;
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qemu_irq psi_irq;
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QEMUTimer *timer;
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MemoryRegion xscom_mbox_regs;
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MemoryRegion xscom_ctrl_regs;
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};
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struct PnvSBEClass {
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DeviceClass parent_class;
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int xscom_ctrl_size;
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int xscom_mbox_size;
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const MemoryRegionOps *xscom_ctrl_ops;
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const MemoryRegionOps *xscom_mbox_ops;
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};
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#endif /* PPC_PNV_SBE_H */
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