Bin Meng 79a412891f target/riscv: gdbstub: Fix dynamic CSR XML generation ... Since commit 605def6eee ("target/riscv: Use the RISCVException enum for CSR operations") the CSR predicate() function was changed to return RISCV_EXCP_NONE instead of 0 for a valid CSR, but it forgot to update the dynamic CSR XML generation codes in gdbstub. Fixes: 605def6eee ("target/riscv: Use the RISCVException enum for CSR operations") Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-06-24 05:00:12 -07:00
..
insn_trans	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
bitmanip_helper.c	target/riscv: rvb: generalized or-combine	2021-06-08 09:59:45 +10:00
cpu_bits.h	target/riscv: fix wfi exception behavior	2021-06-08 09:59:42 +10:00
cpu_helper.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
cpu.h	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
csr.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: gdbstub: Fix dynamic CSR XML generation	2021-06-24 05:00:12 -07:00
helper.h	target/riscv: rvb: generalized or-combine	2021-06-08 09:59:45 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
op_helper.c	target/riscv: fix wfi exception behavior	2021-06-08 09:59:42 +10:00
pmp.c	target/riscv/pmp: Add assert for ePMP operations	2021-06-08 09:59:43 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Use target_ulong for the DisasContext misa	2021-06-24 05:00:12 -07:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00