730 lines
22 KiB
C
730 lines
22 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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static struct XtensaConfigList *xtensa_cores;
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static void xtensa_core_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
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const XtensaConfig *config = data;
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xcc->config = config;
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/* Use num_core_regs to see only non-privileged registers in an unmodified
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* gdb. Use num_regs to see all registers. gdb modification is required
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* for that: reset bit 0 in the 'flags' field of the registers definitions
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* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
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*/
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cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
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}
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void xtensa_finalize_config(XtensaConfig *config)
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{
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unsigned i, n = 0;
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if (config->gdb_regmap.num_regs) {
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return;
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}
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for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
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n += (config->gdb_regmap.reg[i].type != 6);
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}
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config->gdb_regmap.num_regs = n;
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}
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void xtensa_register_core(XtensaConfigList *node)
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{
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TypeInfo type = {
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.parent = TYPE_XTENSA_CPU,
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.class_init = xtensa_core_class_init,
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.class_data = (void *)node->config,
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};
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node->next = xtensa_cores;
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xtensa_cores = node;
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type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
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type_register(&type);
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g_free((gpointer)type.name);
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}
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static uint32_t check_hw_breakpoints(CPUXtensaState *env)
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{
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unsigned i;
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for (i = 0; i < env->config->ndbreak; ++i) {
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if (env->cpu_watchpoint[i] &&
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env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
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return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
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}
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}
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return 0;
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}
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void xtensa_breakpoint_handler(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (cs->watchpoint_hit) {
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if (cs->watchpoint_hit->flags & BP_CPU) {
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uint32_t cause;
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cs->watchpoint_hit = NULL;
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cause = check_hw_breakpoints(env);
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if (cause) {
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debug_exception_env(env, cause);
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}
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cpu_resume_from_signal(cs, NULL);
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}
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}
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}
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XtensaCPU *cpu_xtensa_init(const char *cpu_model)
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{
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ObjectClass *oc;
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XtensaCPU *cpu;
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CPUXtensaState *env;
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oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
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if (oc == NULL) {
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return NULL;
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}
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cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
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env = &cpu->env;
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xtensa_irq_init(env);
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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XtensaConfigList *core = xtensa_cores;
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cpu_fprintf(f, "Available CPUs:\n");
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for (; core; core = core->next) {
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cpu_fprintf(f, " %s\n", core->config->name);
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}
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}
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hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
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&paddr, &page_size, &access) == 0) {
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return paddr;
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}
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if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
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&paddr, &page_size, &access) == 0) {
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return paddr;
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}
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return ~0;
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}
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static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
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{
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if (xtensa_option_enabled(env->config,
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XTENSA_OPTION_RELOCATABLE_VECTOR)) {
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return vector - env->config->vecbase + env->sregs[VECBASE];
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} else {
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return vector;
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}
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}
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/*!
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* Handle penging IRQ.
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* For the high priority interrupt jump to the corresponding interrupt vector.
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* For the level-1 interrupt convert it to either user, kernel or double
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* exception with the 'level-1 interrupt' exception cause.
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*/
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static void handle_interrupt(CPUXtensaState *env)
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{
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int level = env->pending_irq_level;
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if (level > xtensa_get_cintlevel(env) &&
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level <= env->config->nlevel &&
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(env->config->level_mask[level] &
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env->sregs[INTSET] &
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env->sregs[INTENABLE])) {
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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if (level > 1) {
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env->sregs[EPC1 + level - 1] = env->pc;
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env->sregs[EPS2 + level - 2] = env->sregs[PS];
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env->sregs[PS] =
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(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
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env->pc = relocated_vector(env,
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env->config->interrupt_vector[level]);
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} else {
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env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
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if (env->sregs[PS] & PS_EXCM) {
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if (env->config->ndepc) {
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env->sregs[DEPC] = env->pc;
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} else {
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env->sregs[EPC1] = env->pc;
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}
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cs->exception_index = EXC_DOUBLE;
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} else {
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env->sregs[EPC1] = env->pc;
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cs->exception_index =
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(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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}
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env->sregs[PS] |= PS_EXCM;
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}
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env->exception_taken = 1;
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}
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}
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void xtensa_cpu_do_interrupt(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (cs->exception_index == EXC_IRQ) {
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qemu_log_mask(CPU_LOG_INT,
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"%s(EXC_IRQ) level = %d, cintlevel = %d, "
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"pc = %08x, a0 = %08x, ps = %08x, "
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"intset = %08x, intenable = %08x, "
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"ccount = %08x\n",
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__func__, env->pending_irq_level, xtensa_get_cintlevel(env),
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env->pc, env->regs[0], env->sregs[PS],
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env->sregs[INTSET], env->sregs[INTENABLE],
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env->sregs[CCOUNT]);
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handle_interrupt(env);
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}
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switch (cs->exception_index) {
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case EXC_WINDOW_OVERFLOW4:
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case EXC_WINDOW_UNDERFLOW4:
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case EXC_WINDOW_OVERFLOW8:
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case EXC_WINDOW_UNDERFLOW8:
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case EXC_WINDOW_OVERFLOW12:
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case EXC_WINDOW_UNDERFLOW12:
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case EXC_KERNEL:
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case EXC_USER:
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case EXC_DOUBLE:
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case EXC_DEBUG:
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qemu_log_mask(CPU_LOG_INT, "%s(%d) "
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"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
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__func__, cs->exception_index,
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env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
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if (env->config->exception_vector[cs->exception_index]) {
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env->pc = relocated_vector(env,
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env->config->exception_vector[cs->exception_index]);
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env->exception_taken = 1;
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} else {
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qemu_log_mask(CPU_LOG_INT, "%s(pc = %08x) bad exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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}
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break;
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case EXC_IRQ:
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break;
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default:
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qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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break;
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}
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check_interrupts(env);
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}
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bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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cs->exception_index = EXC_IRQ;
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xtensa_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
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const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
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{
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unsigned wi, ei;
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for (wi = 0; wi < tlb->nways; ++wi) {
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for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
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entry[wi][ei].asid = 0;
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entry[wi][ei].variable = true;
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}
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}
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}
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static void reset_tlb_mmu_ways56(CPUXtensaState *env,
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const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
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{
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if (!tlb->varway56) {
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static const xtensa_tlb_entry way5[] = {
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{
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.vaddr = 0xd0000000,
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.paddr = 0,
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.asid = 1,
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.attr = 7,
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.variable = false,
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}, {
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.vaddr = 0xd8000000,
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.paddr = 0,
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.asid = 1,
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.attr = 3,
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.variable = false,
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}
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};
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static const xtensa_tlb_entry way6[] = {
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{
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.vaddr = 0xe0000000,
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.paddr = 0xf0000000,
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.asid = 1,
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.attr = 7,
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.variable = false,
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}, {
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.vaddr = 0xf0000000,
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.paddr = 0xf0000000,
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.asid = 1,
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.attr = 3,
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.variable = false,
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}
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};
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memcpy(entry[5], way5, sizeof(way5));
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memcpy(entry[6], way6, sizeof(way6));
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} else {
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uint32_t ei;
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for (ei = 0; ei < 8; ++ei) {
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entry[6][ei].vaddr = ei << 29;
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entry[6][ei].paddr = ei << 29;
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entry[6][ei].asid = 1;
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entry[6][ei].attr = 3;
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}
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}
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}
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static void reset_tlb_region_way0(CPUXtensaState *env,
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xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
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{
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unsigned ei;
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for (ei = 0; ei < 8; ++ei) {
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entry[0][ei].vaddr = ei << 29;
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entry[0][ei].paddr = ei << 29;
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entry[0][ei].asid = 1;
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entry[0][ei].attr = 2;
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entry[0][ei].variable = true;
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}
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}
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void reset_mmu(CPUXtensaState *env)
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{
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
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env->sregs[RASID] = 0x04030201;
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env->sregs[ITLBCFG] = 0;
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env->sregs[DTLBCFG] = 0;
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env->autorefill_idx = 0;
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reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
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reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
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reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
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reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
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} else {
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reset_tlb_region_way0(env, env->itlb);
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reset_tlb_region_way0(env, env->dtlb);
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}
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}
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static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
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{
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unsigned i;
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for (i = 0; i < 4; ++i) {
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if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
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return i;
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}
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}
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return 0xff;
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}
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/*!
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* Lookup xtensa TLB for the given virtual address.
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* See ISA, 4.6.2.2
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*
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* \param pwi: [out] way index
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* \param pei: [out] entry index
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* \param pring: [out] access ring
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* \return 0 if ok, exception cause code otherwise
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*/
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int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
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uint32_t *pwi, uint32_t *pei, uint8_t *pring)
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{
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const xtensa_tlb *tlb = dtlb ?
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&env->config->dtlb : &env->config->itlb;
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const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
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env->dtlb : env->itlb;
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int nhits = 0;
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unsigned wi;
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for (wi = 0; wi < tlb->nways; ++wi) {
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uint32_t vpn;
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uint32_t ei;
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split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
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if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
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unsigned ring = get_ring(env, entry[wi][ei].asid);
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if (ring < 4) {
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if (++nhits > 1) {
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return dtlb ?
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LOAD_STORE_TLB_MULTI_HIT_CAUSE :
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INST_TLB_MULTI_HIT_CAUSE;
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}
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*pwi = wi;
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*pei = ei;
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*pring = ring;
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}
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}
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}
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return nhits ? 0 :
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(dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
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}
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/*!
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* Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
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* See ISA, 4.6.5.10
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*/
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static unsigned mmu_attr_to_access(uint32_t attr)
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{
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unsigned access = 0;
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if (attr < 12) {
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access |= PAGE_READ;
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if (attr & 0x1) {
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access |= PAGE_EXEC;
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}
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if (attr & 0x2) {
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access |= PAGE_WRITE;
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}
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switch (attr & 0xc) {
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case 0:
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access |= PAGE_CACHE_BYPASS;
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break;
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case 4:
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access |= PAGE_CACHE_WB;
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break;
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case 8:
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access |= PAGE_CACHE_WT;
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break;
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}
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} else if (attr == 13) {
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access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
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}
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return access;
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}
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/*!
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* Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
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* See ISA, 4.6.3.3
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*/
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static unsigned region_attr_to_access(uint32_t attr)
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{
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static const unsigned access[16] = {
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[0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
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[1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
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[2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
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[3] = PAGE_EXEC | PAGE_CACHE_WB,
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[4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
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[5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
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[14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
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};
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return access[attr & 0xf];
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}
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/*!
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* Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
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* See ISA, A.2.14 The Cache Attribute Register
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*/
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static unsigned cacheattr_attr_to_access(uint32_t attr)
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{
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static const unsigned access[16] = {
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[0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
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[1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
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[2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
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[3] = PAGE_EXEC | PAGE_CACHE_WB,
|
|
[4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
|
|
[14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
|
|
};
|
|
|
|
return access[attr & 0xf];
|
|
}
|
|
|
|
static bool is_access_granted(unsigned access, int is_write)
|
|
{
|
|
switch (is_write) {
|
|
case 0:
|
|
return access & PAGE_READ;
|
|
|
|
case 1:
|
|
return access & PAGE_WRITE;
|
|
|
|
case 2:
|
|
return access & PAGE_EXEC;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
|
|
|
|
static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access,
|
|
bool may_lookup_pt)
|
|
{
|
|
bool dtlb = is_write != 2;
|
|
uint32_t wi;
|
|
uint32_t ei;
|
|
uint8_t ring;
|
|
uint32_t vpn;
|
|
uint32_t pte;
|
|
const xtensa_tlb_entry *entry = NULL;
|
|
xtensa_tlb_entry tmp_entry;
|
|
int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
|
|
|
|
if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
|
|
may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
|
|
ring = (pte >> 4) & 0x3;
|
|
wi = 0;
|
|
split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
|
|
|
|
if (update_tlb) {
|
|
wi = ++env->autorefill_idx & 0x3;
|
|
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
|
|
env->sregs[EXCVADDR] = vaddr;
|
|
qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
|
|
__func__, vaddr, vpn, pte);
|
|
} else {
|
|
xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
|
|
entry = &tmp_entry;
|
|
}
|
|
ret = 0;
|
|
}
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
|
|
if (entry == NULL) {
|
|
entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
}
|
|
|
|
if (ring < mmu_idx) {
|
|
return dtlb ?
|
|
LOAD_STORE_PRIVILEGE_CAUSE :
|
|
INST_FETCH_PRIVILEGE_CAUSE;
|
|
}
|
|
|
|
*access = mmu_attr_to_access(entry->attr) &
|
|
~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
|
|
if (!is_access_granted(*access, is_write)) {
|
|
return dtlb ?
|
|
(is_write ?
|
|
STORE_PROHIBITED_CAUSE :
|
|
LOAD_PROHIBITED_CAUSE) :
|
|
INST_FETCH_PROHIBITED_CAUSE;
|
|
}
|
|
|
|
*paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
|
|
*page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
|
|
{
|
|
CPUState *cs = CPU(xtensa_env_get_cpu(env));
|
|
uint32_t paddr;
|
|
uint32_t page_size;
|
|
unsigned access;
|
|
uint32_t pt_vaddr =
|
|
(env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
|
|
int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
|
|
&paddr, &page_size, &access, false);
|
|
|
|
qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
|
|
__func__, vaddr, ret ? ~0 : paddr);
|
|
|
|
if (ret == 0) {
|
|
*pte = ldl_phys(cs->as, paddr);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int get_physical_addr_region(CPUXtensaState *env,
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access)
|
|
{
|
|
bool dtlb = is_write != 2;
|
|
uint32_t wi = 0;
|
|
uint32_t ei = (vaddr >> 29) & 0x7;
|
|
const xtensa_tlb_entry *entry =
|
|
xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
|
|
*access = region_attr_to_access(entry->attr);
|
|
if (!is_access_granted(*access, is_write)) {
|
|
return dtlb ?
|
|
(is_write ?
|
|
STORE_PROHIBITED_CAUSE :
|
|
LOAD_PROHIBITED_CAUSE) :
|
|
INST_FETCH_PROHIBITED_CAUSE;
|
|
}
|
|
|
|
*paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
|
|
*page_size = ~REGION_PAGE_MASK + 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*!
|
|
* Convert virtual address to physical addr.
|
|
* MMU may issue pagewalk and change xtensa autorefill TLB way entry.
|
|
*
|
|
* \return 0 if ok, exception cause code otherwise
|
|
*/
|
|
int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access)
|
|
{
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
return get_physical_addr_mmu(env, update_tlb,
|
|
vaddr, is_write, mmu_idx, paddr, page_size, access, true);
|
|
} else if (xtensa_option_bits_enabled(env->config,
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
|
|
return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
|
|
paddr, page_size, access);
|
|
} else {
|
|
*paddr = vaddr;
|
|
*page_size = TARGET_PAGE_SIZE;
|
|
*access = cacheattr_attr_to_access(
|
|
env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
|
|
CPUXtensaState *env, bool dtlb)
|
|
{
|
|
unsigned wi, ei;
|
|
const xtensa_tlb *conf =
|
|
dtlb ? &env->config->dtlb : &env->config->itlb;
|
|
unsigned (*attr_to_access)(uint32_t) =
|
|
xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
|
|
mmu_attr_to_access : region_attr_to_access;
|
|
|
|
for (wi = 0; wi < conf->nways; ++wi) {
|
|
uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
|
|
const char *sz_text;
|
|
bool print_header = true;
|
|
|
|
if (sz >= 0x100000) {
|
|
sz >>= 20;
|
|
sz_text = "MB";
|
|
} else {
|
|
sz >>= 10;
|
|
sz_text = "KB";
|
|
}
|
|
|
|
for (ei = 0; ei < conf->way_size[wi]; ++ei) {
|
|
const xtensa_tlb_entry *entry =
|
|
xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
|
|
if (entry->asid) {
|
|
static const char * const cache_text[8] = {
|
|
[PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
|
|
[PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
|
|
[PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
|
|
[PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
|
|
};
|
|
unsigned access = attr_to_access(entry->attr);
|
|
unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
|
|
PAGE_CACHE_SHIFT;
|
|
|
|
if (print_header) {
|
|
print_header = false;
|
|
cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
|
|
cpu_fprintf(f,
|
|
"\tVaddr Paddr ASID Attr RWX Cache\n"
|
|
"\t---------- ---------- ---- ---- --- -------\n");
|
|
}
|
|
cpu_fprintf(f,
|
|
"\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
|
|
entry->vaddr,
|
|
entry->paddr,
|
|
entry->asid,
|
|
entry->attr,
|
|
(access & PAGE_READ) ? 'R' : '-',
|
|
(access & PAGE_WRITE) ? 'W' : '-',
|
|
(access & PAGE_EXEC) ? 'X' : '-',
|
|
cache_text[cache_idx] ? cache_text[cache_idx] :
|
|
"Invalid");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
|
|
{
|
|
if (xtensa_option_bits_enabled(env->config,
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
|
|
|
|
cpu_fprintf(f, "ITLB:\n");
|
|
dump_tlb(f, cpu_fprintf, env, false);
|
|
cpu_fprintf(f, "\nDTLB:\n");
|
|
dump_tlb(f, cpu_fprintf, env, true);
|
|
} else {
|
|
cpu_fprintf(f, "No TLB for this CPU core\n");
|
|
}
|
|
}
|