50f57e09fd
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122913.19561-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
335 lines
11 KiB
C
335 lines
11 KiB
C
/*
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* ARM gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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typedef struct RegisterSysregXmlParam {
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CPUState *cs;
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GString *s;
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int n;
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} RegisterSysregXmlParam;
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/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
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whatever the target description contains. Due to a historical mishap
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the FPA registers appear in between core integer regs and the CPSR.
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We hack round this by giving the FPA regs zero size when talking to a
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newer gdb. */
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int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (n < 16) {
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/* Core integer register. */
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return gdb_get_reg32(mem_buf, env->regs[n]);
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}
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if (n < 24) {
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/* FPA registers. */
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if (gdb_has_xml) {
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return 0;
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}
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return gdb_get_zeroes(mem_buf, 12);
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}
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switch (n) {
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case 24:
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/* FPA status register. */
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if (gdb_has_xml) {
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return 0;
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}
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return gdb_get_reg32(mem_buf, 0);
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case 25:
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/* CPSR, or XPSR for M-profile */
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if (arm_feature(env, ARM_FEATURE_M)) {
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return gdb_get_reg32(mem_buf, xpsr_read(env));
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} else {
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return gdb_get_reg32(mem_buf, cpsr_read(env));
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}
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}
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/* Unknown register. */
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return 0;
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}
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int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t tmp;
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tmp = ldl_p(mem_buf);
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/* Mask out low bit of PC to workaround gdb bugs. This will probably
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cause problems if we ever implement the Jazelle DBX extensions. */
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if (n == 15) {
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tmp &= ~1;
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}
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if (n < 16) {
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/* Core integer register. */
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env->regs[n] = tmp;
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return 4;
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}
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if (n < 24) { /* 16-23 */
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/* FPA registers (ignored). */
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if (gdb_has_xml) {
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return 0;
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}
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return 12;
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}
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switch (n) {
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case 24:
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/* FPA status register (ignored). */
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if (gdb_has_xml) {
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return 0;
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}
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return 4;
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case 25:
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/* CPSR, or XPSR for M-profile */
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if (arm_feature(env, ARM_FEATURE_M)) {
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/*
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* Don't allow writing to XPSR.Exception as it can cause
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* a transition into or out of handler mode (it's not
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* writeable via the MSR insn so this is a reasonable
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* restriction). Other fields are safe to update.
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*/
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xpsr_write(env, tmp, ~XPSR_EXCP);
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} else {
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cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
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}
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return 4;
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}
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/* Unknown register. */
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return 0;
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}
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static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
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ARMCPRegInfo *ri, uint32_t ri_key,
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int bitsize, int regnum)
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{
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g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
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g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
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g_string_append_printf(s, " regnum=\"%d\"", regnum);
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g_string_append_printf(s, " group=\"cp_regs\"/>");
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dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
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dyn_xml->num++;
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}
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static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
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gpointer p)
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{
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uint32_t ri_key = *(uint32_t *)key;
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ARMCPRegInfo *ri = value;
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RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
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GString *s = param->s;
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ARMCPU *cpu = ARM_CPU(param->cs);
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CPUARMState *env = &cpu->env;
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DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;
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if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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if (ri->state == ARM_CP_STATE_AA64) {
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arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
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param->n++);
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}
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} else {
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if (ri->state == ARM_CP_STATE_AA32) {
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if (!arm_feature(env, ARM_FEATURE_EL3) &&
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(ri->secure & ARM_CP_SECSTATE_S)) {
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return;
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}
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if (ri->type & ARM_CP_64BIT) {
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arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
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param->n++);
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} else {
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arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
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param->n++);
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}
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}
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}
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}
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}
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int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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RegisterSysregXmlParam param = {cs, s, base_reg};
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cpu->dyn_sysreg_xml.num = 0;
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cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
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g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m);
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g_string_append_printf(s, "</feature>");
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cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
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return cpu->dyn_sysreg_xml.num;
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}
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struct TypeSize {
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const char *gdb_type;
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int size;
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const char sz, suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", 128, 'q', 'u' },
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{ "int128", 128, 'q', 's' },
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/* 64 bit */
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{ "uint64", 64, 'd', 'u' },
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{ "int64", 64, 'd', 's' },
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{ "ieee_double", 64, 'd', 'f' },
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/* 32 bit */
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{ "uint32", 32, 's', 'u' },
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{ "int32", 32, 's', 's' },
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{ "ieee_single", 32, 's', 'f' },
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/* 16 bit */
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{ "uint16", 16, 'h', 'u' },
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{ "int16", 16, 'h', 's' },
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/*
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* TODO: currently there is no reliable way of telling
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* if the remote gdb actually understands ieee_half so
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* we don't expose it in the target description for now.
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* { "ieee_half", 16, 'h', 'f' },
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*/
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/* bytes */
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{ "uint8", 8, 'b', 'u' },
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{ "int8", 8, 'b', 's' },
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};
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
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g_autoptr(GString) ts = g_string_new("");
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int i, bits, reg_width = (cpu->sve_max_vq * 128);
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info->num = 0;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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g_string_printf(ts, "vq%d%c%c", count,
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vec_lanes[i].sz, vec_lanes[i].suffix);
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g_string_append_printf(s,
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"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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ts->str, vec_lanes[i].gdb_type, count);
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}
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/*
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* Now define a union for each size group containing unsigned and
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* signed and potentially float versions of each size from 128 to
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* 8 bits.
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*/
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for (bits = 128; bits >= 8; bits /= 2) {
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int count = reg_width / bits;
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g_string_append_printf(s, "<union id=\"vq%dn\">", count);
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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if (vec_lanes[i].size == bits) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
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vec_lanes[i].suffix,
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count,
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vec_lanes[i].sz, vec_lanes[i].suffix);
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}
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}
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g_string_append(s, "</union>");
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}
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/* And now the final union of unions */
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g_string_append(s, "<union id=\"vq\">");
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for (bits = 128; bits >= 8; bits /= 2) {
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int count = reg_width / bits;
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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if (vec_lanes[i].size == bits) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
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vec_lanes[i].sz, count);
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break;
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}
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}
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}
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g_string_append(s, "</union>");
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/* Then define each register in parts for each vq */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"z%d\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"vq\"/>",
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i, reg_width, base_reg++);
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info->num++;
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}
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/* fpscr & status registers */
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g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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info->num += 2;
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/*
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* Predicate registers aren't so big they are worth splitting up
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* but we do need to define a type to hold the array of quad
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* references.
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*/
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g_string_append_printf(s,
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"<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
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cpu->sve_max_vq);
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for (i = 0; i < 16; i++) {
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g_string_append_printf(s,
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"<reg name=\"p%d\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"vqp\"/>",
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i, cpu->sve_max_vq * 16, base_reg++);
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info->num++;
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}
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g_string_append_printf(s,
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"<reg name=\"ffr\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"vqp\"/>",
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cpu->sve_max_vq * 16, base_reg++);
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g_string_append_printf(s,
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"<reg name=\"vg\" bitsize=\"64\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"uint32\"/>",
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base_reg++);
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info->num += 2;
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g_string_append_printf(s, "</feature>");
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cpu->dyn_svereg_xml.desc = g_string_free(s, false);
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return cpu->dyn_svereg_xml.num;
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}
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const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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if (strcmp(xmlname, "system-registers.xml") == 0) {
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return cpu->dyn_sysreg_xml.desc;
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} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
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return cpu->dyn_svereg_xml.desc;
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}
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return NULL;
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}
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