2d03b49c3f
* AArch64 system mode support; this is all the CPU emulation code
but not the virt board support
* cadence_ttc match register bugfix
* Allwinner A10 PIC, PIT and ethernet fixes
[with update to avoid duplicate typedef]
* zynq-slcr rewrite
* cadence_gem bugfix
* fix for SMLALD/SMLSLD insn in A32
* fix for SQXTUN in A64
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABCAAGBQJTUDstAAoJEDwlJe0UNgzeX4kP/RZ/ndirQRDDLqFUMju1IMBo
Asx+ulM8tU+gROQ1ZMAHEHO7UUXKWTKvBsTgbLj4nQB0lzpGnmLK3ct6HED+6VYL
8UbZUytdAbkQkpL5CHf2vgt4MwOkSXN79QmkQLTJkEJU2uRGqLIV8ZM4dlF6Eql0
Pwb+aeyHjbB57MdhiiVco3shl4sbs3ocLjUT4ARcieuWG3tF+3gU/QiOdZI7sdZj
qbQTyAELzadW/FZOswWyXqJxmlIVuEGfIkFuWXQriv0+NkgVk3NemlmQYlVb1MXF
954IGkYcWo1KSTtNC0d+4QmqWCZle75LsVJ9oniiAxs8TozWIEv0gexcigH+1trf
Hq/RcY+hPFAqKLg6gRQvP3FlaPQa+QFcQsm1U2qv2dUsNiI9X6Ru8PfSt2FYhcB6
SryYAoy11jO/n9rkruISgskgeWAd8M0oUlND01PIS68jhlR/EUET+wye18UTOrDY
TjBPS0/4ab7EhJ/6Sqvuo+qyDgq+gRMsBUgbopf0BQC2RLPlFsHeYYI0qNdxa4hp
QZ/5OSUUFQKekJmcm/F7VP9egVqbbluzQ2H+BuCGraqAzzmWK5xQq8+vT5DVFAS/
vvbz8I21giNSYBAZTm98w/gDO7Lf6YH5wBtlzE1qjRHLWp3V1w9kcuoR1J1DhyUF
1GUqny1Ay+inhWfNAtRf
=8sP7
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140417-1' into staging
target-arm queue:
* AArch64 system mode support; this is all the CPU emulation code
but not the virt board support
* cadence_ttc match register bugfix
* Allwinner A10 PIC, PIT and ethernet fixes
[with update to avoid duplicate typedef]
* zynq-slcr rewrite
* cadence_gem bugfix
* fix for SMLALD/SMLSLD insn in A32
* fix for SQXTUN in A64
# gpg: Signature made Thu 17 Apr 2014 21:35:57 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20140417-1: (51 commits)
target-arm: A64: fix unallocated test of scalar SQXTUN
arm: translate.c: Fix smlald Instruction
net: cadence_gem: Make phy respond to broadcast
misc: zynq_slcr: Make DB_PRINTs always compile
misc: zynq_slcr: Convert SBD::init to object init
misc: zynq-slcr: Rewrite
allwinner-emac: update irq status after writes to interrupt registers
allwinner-emac: set autonegotiation complete bit on link up
allwinner-a10-pit: implement prescaler and source selection
allwinner-a10-pit: use level triggered interrupts
allwinner-a10-pit: avoid generation of spurious interrupts
allwinner-a10-pic: fix behaviour of pending register
allwinner-a10-pic: set vector address when an interrupt is pending
timer: cadence_ttc: Fix match register write logic
target-arm/gdbstub64.c: remove useless 'break' statement.
target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
target-arm: Make Cortex-A15 CBAR read-only
target-arm: Implement CBAR for Cortex-A57
target-arm: Implement Cortex-A57 implementation-defined system registers
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team