734c44ea13
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead of the separate arrays and adjust ppc4xx_sdram_init() and ppc440_sdram_init() accordingly as well as machines using these. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
190 lines
4.5 KiB
C
190 lines
4.5 KiB
C
/*
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* QEMU PowerPC 405 shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef PPC405_H
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#define PPC405_H
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#include "qom/object.h"
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#include "hw/ppc/ppc4xx.h"
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#include "hw/intc/ppc-uic.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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/* PLB to OPB bridge */
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#define TYPE_PPC405_POB "ppc405-pob"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
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struct Ppc405PobState {
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Ppc4xxDcrDeviceState parent_obj;
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uint32_t bear;
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uint32_t besr0;
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uint32_t besr1;
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};
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/* OPB arbitrer */
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#define TYPE_PPC405_OPBA "ppc405-opba"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
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struct Ppc405OpbaState {
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SysBusDevice parent_obj;
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MemoryRegion io;
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uint8_t cr;
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uint8_t pr;
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};
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/* DMA controller */
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#define TYPE_PPC405_DMA "ppc405-dma"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
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struct Ppc405DmaState {
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Ppc4xxDcrDeviceState parent_obj;
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qemu_irq irqs[4];
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uint32_t cr[4];
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uint32_t ct[4];
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uint32_t da[4];
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uint32_t sa[4];
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uint32_t sg[4];
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uint32_t sr;
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uint32_t sgc;
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uint32_t slp;
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uint32_t pol;
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};
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/* GPIO */
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#define TYPE_PPC405_GPIO "ppc405-gpio"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
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struct Ppc405GpioState {
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SysBusDevice parent_obj;
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MemoryRegion io;
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uint32_t or;
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uint32_t tcr;
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uint32_t osrh;
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uint32_t osrl;
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uint32_t tsrh;
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uint32_t tsrl;
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uint32_t odr;
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uint32_t ir;
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uint32_t rr1;
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uint32_t isr1h;
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uint32_t isr1l;
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};
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/* On Chip Memory */
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#define TYPE_PPC405_OCM "ppc405-ocm"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
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struct Ppc405OcmState {
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Ppc4xxDcrDeviceState parent_obj;
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MemoryRegion ram;
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MemoryRegion isarc_ram;
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MemoryRegion dsarc_ram;
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uint32_t isarc;
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uint32_t isacntl;
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uint32_t dsarc;
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uint32_t dsacntl;
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};
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/* General purpose timers */
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#define TYPE_PPC405_GPT "ppc405-gpt"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
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struct Ppc405GptState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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int64_t tb_offset;
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uint32_t tb_freq;
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QEMUTimer *timer;
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qemu_irq irqs[5];
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uint32_t oe;
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uint32_t ol;
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uint32_t im;
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uint32_t is;
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uint32_t ie;
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uint32_t comp[5];
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uint32_t mask[5];
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};
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#define TYPE_PPC405_CPC "ppc405-cpc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
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enum {
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PPC405EP_CPU_CLK = 0,
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PPC405EP_PLB_CLK = 1,
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PPC405EP_OPB_CLK = 2,
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PPC405EP_EBC_CLK = 3,
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PPC405EP_MAL_CLK = 4,
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PPC405EP_PCI_CLK = 5,
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PPC405EP_UART0_CLK = 6,
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PPC405EP_UART1_CLK = 7,
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PPC405EP_CLK_NB = 8,
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};
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struct Ppc405CpcState {
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Ppc4xxDcrDeviceState parent_obj;
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uint32_t sysclk;
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clk_setup_t clk_setup[PPC405EP_CLK_NB];
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uint32_t boot;
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uint32_t epctl;
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uint32_t pllmr[2];
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uint32_t ucr;
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uint32_t srr;
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uint32_t jtagid;
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uint32_t pci;
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/* Clock and power management */
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uint32_t er;
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uint32_t fr;
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uint32_t sr;
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};
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#define TYPE_PPC405_SOC "ppc405-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
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struct Ppc405SoCState {
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/* Private */
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DeviceState parent_obj;
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/* Public */
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Ppc4xxSdramBank ram_banks[2];
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MemoryRegion *dram_mr;
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hwaddr ram_size;
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PowerPCCPU cpu;
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PPCUIC uic;
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Ppc405CpcState cpc;
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Ppc405GptState gpt;
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Ppc405OcmState ocm;
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Ppc405GpioState gpio;
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Ppc405DmaState dma;
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PPC4xxI2CState i2c;
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Ppc4xxEbcState ebc;
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Ppc405OpbaState opba;
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Ppc405PobState pob;
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Ppc4xxPlbState plb;
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Ppc4xxMalState mal;
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};
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#endif /* PPC405_H */
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