Thomas Huth e89720b116 tcg/ppc64: Fix zero extension code generation bug for ppc64 host ... The ppc64 code generation backend uses an rldicr (Rotate Left Double Immediate and Clear Right) instruction to implement zero extension of a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However this is wrong - this instruction clears specified low bits of the value, instead of high bits as we require for a zero extension. It should instead use an rldicl (Rotate Left Double Immediate and Clear Left) instruction. Presumably amongst other things, this causes the SLOF firmware image used with -M pseries to not boot on a ppc64 host. It appears this bug was exposed by commit 0bf1dbdcc9 (tcg/ppc64: fix 16/32 mixup) which enabled the use of the op_ext32u_i64 operation on the ppc64 backend. Signed-off-by: Thomas Huth <thuth@de.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>		2011-09-09 19:07:06 +04:00
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tcg-target.c	tcg/ppc64: Fix zero extension code generation bug for ppc64 host	2011-09-09 19:07:06 +04:00
tcg-target.h	tcg/ppc64: fix 16/32 mixup	2011-08-22 18:26:15 +04:00