8a863c8120
Commit ba1ba5cca introduce the ARM_CPU_TYPE_NAME() macro.
Unify the code base by use it in all places.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190823143249.8096-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/*
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* QEMU model of the Canon DIGIC SoC.
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*
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* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This model is based on reverse engineering efforts
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* made by CHDK (http://chdk.wikia.com) and
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* Magic Lantern (http://www.magiclantern.fm) projects
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* contributors.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/arm/digic.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/sysemu.h"
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#define DIGIC4_TIMER_BASE(n) (0xc0210000 + (n) * 0x100)
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#define DIGIC_UART_BASE 0xc0800000
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static void digic_init(Object *obj)
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{
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DigicState *s = DIGIC(obj);
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int i;
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object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
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ARM_CPU_TYPE_NAME("arm946"),
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&error_abort, NULL);
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for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
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#define DIGIC_TIMER_NAME_MLEN 11
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char name[DIGIC_TIMER_NAME_MLEN];
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snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
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sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
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TYPE_DIGIC_TIMER);
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}
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sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
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TYPE_DIGIC_UART);
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}
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static void digic_realize(DeviceState *dev, Error **errp)
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{
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DigicState *s = DIGIC(dev);
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Error *err = NULL;
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SysBusDevice *sbd;
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int i;
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object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
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object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sbd = SYS_BUS_DEVICE(&s->timer[i]);
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sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
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}
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qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
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object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sbd = SYS_BUS_DEVICE(&s->uart);
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sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
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}
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static void digic_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = digic_realize;
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/* Reason: Uses serial_hds in the realize function --> not usable twice */
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dc->user_creatable = false;
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}
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static const TypeInfo digic_type_info = {
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.name = TYPE_DIGIC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(DigicState),
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.instance_init = digic_init,
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.class_init = digic_class_init,
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};
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static void digic_register_types(void)
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{
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type_register_static(&digic_type_info);
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}
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type_init(digic_register_types)
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