qemu/target
Paolo Bonzini 2b55e479e6 target/i386: fix operand size for VCOMI/VUCOMI instructions
Compared to other SSE instructions, VUCOMISx and VCOMISx are different:
the single and double precision versions are distinguished through a
prefix, however they use no-prefix and 0x66 for SS and SD respectively.
Scalar values usually are associated with 0xF2 and 0xF3.

Because of these, they incorrectly perform a 128-bit memory load instead
of a 32- or 64-bit load.  Fix this by writing a custom decoding function.

I tested that the reproducer is fixed and the test-avx output does not
change.

Reported-by: Gabriele Svelto <gsvelto@mozilla.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1637
Fixes: f8d19eec0d ("target/i386: reimplement 0x0f 0x28-0x2f, add AVX", 2022-10-18)
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18 08:53:50 +02:00
..
alpha target/alpha: Use MO_ALIGN where required 2023-05-05 17:05:58 +01:00
arm target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check 2023-05-12 16:01:25 +01:00
avr target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* 2023-05-05 17:05:28 +01:00
cris target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_* 2023-05-05 17:05:28 +01:00
hexagon target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* 2023-05-05 17:05:28 +01:00
hppa target/hppa: Use MO_ALIGN for system UNALIGN() 2023-05-05 17:05:58 +01:00
i386 target/i386: fix operand size for VCOMI/VUCOMI instructions 2023-05-18 08:53:50 +02:00
loongarch target/loongarch: Do not include tcg-ldst.h 2023-05-11 09:53:41 +01:00
m68k target/m68k: Fix gen_load_fp for OS_LONG 2023-05-11 09:49:25 +01:00
microblaze target/microblaze: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
mips target/mips: Use MO_ALIGN instead of 0 2023-05-11 09:53:41 +01:00
nios2 target/nios2: Remove TARGET_ALIGNED_ONLY 2023-05-11 09:53:41 +01:00
openrisc target/openrisc: Setup FPU for detecting tininess before rounding 2023-05-11 15:40:28 +01:00
ppc tcg: ppc64: Fix mask generation for vextractdm 2023-05-05 12:34:22 -03:00
riscv target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
rx target/rx: Avoid tcg_const_i32 2023-03-13 06:44:37 -07:00
s390x target/s390x: Fix EXECUTE of relative branches 2023-05-16 09:14:18 +02:00
sh4 target/sh4: Use MO_ALIGN where required 2023-05-11 09:53:41 +01:00
sparc target/sparc: Use cpu_ld*_code_mmu 2023-05-05 17:09:47 +01:00
tricore target/tricore: Use min/max for saturate 2023-03-13 07:03:39 -07:00
xtensa target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_* 2023-05-05 17:05:29 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00