2b41f10e18
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
487 lines
12 KiB
C
487 lines
12 KiB
C
/*
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* Alpha emulation cpu helpers for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "cpu.h"
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#include "softfloat.h"
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uint64_t cpu_alpha_load_fpcr (CPUState *env)
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{
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uint64_t r = 0;
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uint8_t t;
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t = env->fpcr_exc_status;
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if (t) {
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r = FPCR_SUM;
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if (t & float_flag_invalid) {
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r |= FPCR_INV;
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}
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if (t & float_flag_divbyzero) {
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r |= FPCR_DZE;
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}
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if (t & float_flag_overflow) {
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r |= FPCR_OVF;
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}
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if (t & float_flag_underflow) {
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r |= FPCR_UNF;
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}
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if (t & float_flag_inexact) {
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r |= FPCR_INE;
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}
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}
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t = env->fpcr_exc_mask;
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if (t & float_flag_invalid) {
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r |= FPCR_INVD;
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}
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if (t & float_flag_divbyzero) {
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r |= FPCR_DZED;
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}
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if (t & float_flag_overflow) {
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r |= FPCR_OVFD;
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}
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if (t & float_flag_underflow) {
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r |= FPCR_UNFD;
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}
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if (t & float_flag_inexact) {
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r |= FPCR_INED;
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}
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switch (env->fpcr_dyn_round) {
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case float_round_nearest_even:
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r |= FPCR_DYN_NORMAL;
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break;
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case float_round_down:
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r |= FPCR_DYN_MINUS;
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break;
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case float_round_up:
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r |= FPCR_DYN_PLUS;
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break;
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case float_round_to_zero:
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r |= FPCR_DYN_CHOPPED;
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break;
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}
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if (env->fpcr_dnz) {
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r |= FPCR_DNZ;
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}
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if (env->fpcr_dnod) {
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r |= FPCR_DNOD;
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}
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if (env->fpcr_undz) {
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r |= FPCR_UNDZ;
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}
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return r;
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}
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void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
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{
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uint8_t t;
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t = 0;
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if (val & FPCR_INV) {
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t |= float_flag_invalid;
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}
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if (val & FPCR_DZE) {
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t |= float_flag_divbyzero;
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}
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if (val & FPCR_OVF) {
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t |= float_flag_overflow;
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}
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if (val & FPCR_UNF) {
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t |= float_flag_underflow;
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}
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if (val & FPCR_INE) {
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t |= float_flag_inexact;
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}
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env->fpcr_exc_status = t;
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t = 0;
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if (val & FPCR_INVD) {
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t |= float_flag_invalid;
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}
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if (val & FPCR_DZED) {
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t |= float_flag_divbyzero;
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}
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if (val & FPCR_OVFD) {
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t |= float_flag_overflow;
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}
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if (val & FPCR_UNFD) {
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t |= float_flag_underflow;
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}
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if (val & FPCR_INED) {
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t |= float_flag_inexact;
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}
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env->fpcr_exc_mask = t;
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switch (val & FPCR_DYN_MASK) {
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case FPCR_DYN_CHOPPED:
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t = float_round_to_zero;
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break;
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case FPCR_DYN_MINUS:
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t = float_round_down;
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break;
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case FPCR_DYN_NORMAL:
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t = float_round_nearest_even;
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break;
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case FPCR_DYN_PLUS:
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t = float_round_up;
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break;
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}
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env->fpcr_dyn_round = t;
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env->fpcr_flush_to_zero
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= (val & (FPCR_UNDZ|FPCR_UNFD)) == (FPCR_UNDZ|FPCR_UNFD);
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env->fpcr_dnz = (val & FPCR_DNZ) != 0;
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env->fpcr_dnod = (val & FPCR_DNOD) != 0;
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env->fpcr_undz = (val & FPCR_UNDZ) != 0;
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}
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#if defined(CONFIG_USER_ONLY)
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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env->exception_index = EXCP_MMFAULT;
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env->trap_arg0 = address;
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return 1;
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}
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#else
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void swap_shadow_regs(CPUState *env)
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{
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uint64_t i0, i1, i2, i3, i4, i5, i6, i7;
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i0 = env->ir[8];
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i1 = env->ir[9];
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i2 = env->ir[10];
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i3 = env->ir[11];
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i4 = env->ir[12];
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i5 = env->ir[13];
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i6 = env->ir[14];
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i7 = env->ir[25];
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env->ir[8] = env->shadow[0];
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env->ir[9] = env->shadow[1];
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env->ir[10] = env->shadow[2];
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env->ir[11] = env->shadow[3];
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env->ir[12] = env->shadow[4];
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env->ir[13] = env->shadow[5];
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env->ir[14] = env->shadow[6];
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env->ir[25] = env->shadow[7];
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env->shadow[0] = i0;
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env->shadow[1] = i1;
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env->shadow[2] = i2;
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env->shadow[3] = i3;
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env->shadow[4] = i4;
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env->shadow[5] = i5;
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env->shadow[6] = i6;
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env->shadow[7] = i7;
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}
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/* Returns the OSF/1 entMM failure indication, or -1 on success. */
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static int get_physical_address(CPUState *env, target_ulong addr,
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int prot_need, int mmu_idx,
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target_ulong *pphys, int *pprot)
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{
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target_long saddr = addr;
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target_ulong phys = 0;
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target_ulong L1pte, L2pte, L3pte;
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target_ulong pt, index;
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int prot = 0;
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int ret = MM_K_ACV;
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/* Ensure that the virtual address is properly sign-extended from
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the last implemented virtual address bit. */
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if (saddr >> TARGET_VIRT_ADDR_SPACE_BITS != saddr >> 63) {
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goto exit;
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}
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/* Translate the superpage. */
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/* ??? When we do more than emulate Unix PALcode, we'll need to
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determine which KSEG is actually active. */
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if (saddr < 0 && ((saddr >> 41) & 3) == 2) {
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/* User-space cannot access KSEG addresses. */
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if (mmu_idx != MMU_KERNEL_IDX) {
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goto exit;
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}
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/* For the benefit of the Typhoon chipset, move bit 40 to bit 43.
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We would not do this if the 48-bit KSEG is enabled. */
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phys = saddr & ((1ull << 40) - 1);
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phys |= (saddr & (1ull << 40)) << 3;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = -1;
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goto exit;
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}
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/* Interpret the page table exactly like PALcode does. */
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pt = env->ptbr;
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/* L1 page table read. */
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index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
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L1pte = ldq_phys(pt + index*8);
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if (unlikely((L1pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
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if (unlikely((L1pte & PTE_KRE) == 0)) {
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goto exit;
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}
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pt = L1pte >> 32 << TARGET_PAGE_BITS;
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/* L2 page table read. */
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index = (addr >> (TARGET_PAGE_BITS + 10)) & 0x3ff;
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L2pte = ldq_phys(pt + index*8);
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if (unlikely((L2pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
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if (unlikely((L2pte & PTE_KRE) == 0)) {
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goto exit;
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}
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pt = L2pte >> 32 << TARGET_PAGE_BITS;
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/* L3 page table read. */
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index = (addr >> TARGET_PAGE_BITS) & 0x3ff;
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L3pte = ldq_phys(pt + index*8);
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phys = L3pte >> 32 << TARGET_PAGE_BITS;
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if (unlikely((L3pte & PTE_VALID) == 0)) {
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ret = MM_K_TNV;
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goto exit;
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}
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#if PAGE_READ != 1 || PAGE_WRITE != 2 || PAGE_EXEC != 4
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# error page bits out of date
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#endif
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/* Check access violations. */
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if (L3pte & (PTE_KRE << mmu_idx)) {
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prot |= PAGE_READ | PAGE_EXEC;
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}
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if (L3pte & (PTE_KWE << mmu_idx)) {
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prot |= PAGE_WRITE;
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}
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if (unlikely((prot & prot_need) == 0 && prot_need)) {
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goto exit;
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}
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/* Check fault-on-operation violations. */
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prot &= ~(L3pte >> 1);
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ret = -1;
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if (unlikely((prot & prot_need) == 0)) {
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ret = (prot_need & PAGE_EXEC ? MM_K_FOE :
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prot_need & PAGE_WRITE ? MM_K_FOW :
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prot_need & PAGE_READ ? MM_K_FOR : -1);
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}
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exit:
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*pphys = phys;
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*pprot = prot;
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return ret;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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target_ulong phys;
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int prot, fail;
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fail = get_physical_address(env, addr, 0, 0, &phys, &prot);
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return (fail >= 0 ? -1 : phys);
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}
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int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
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int mmu_idx, int is_softmmu)
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{
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target_ulong phys;
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int prot, fail;
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fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
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if (unlikely(fail >= 0)) {
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env->exception_index = EXCP_MMFAULT;
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env->trap_arg0 = addr;
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env->trap_arg1 = fail;
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env->trap_arg2 = (rw == 2 ? -1 : rw);
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return 1;
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}
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tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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#endif /* USER_ONLY */
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void do_interrupt (CPUState *env)
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{
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int i = env->exception_index;
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static int count;
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const char *name = "<unknown>";
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switch (i) {
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case EXCP_RESET:
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name = "reset";
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break;
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case EXCP_MCHK:
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name = "mchk";
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break;
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case EXCP_SMP_INTERRUPT:
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name = "smp_interrupt";
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break;
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case EXCP_CLK_INTERRUPT:
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name = "clk_interrupt";
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break;
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case EXCP_DEV_INTERRUPT:
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name = "dev_interrupt";
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break;
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case EXCP_MMFAULT:
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name = "mmfault";
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break;
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case EXCP_UNALIGN:
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name = "unalign";
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break;
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case EXCP_OPCDEC:
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name = "opcdec";
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break;
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case EXCP_ARITH:
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name = "arith";
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break;
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case EXCP_FEN:
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name = "fen";
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break;
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case EXCP_CALL_PAL:
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name = "call_pal";
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break;
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case EXCP_STL_C:
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name = "stl_c";
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break;
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case EXCP_STQ_C:
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name = "stq_c";
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break;
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}
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qemu_log("INT %6d: %s(%#x) pc=%016" PRIx64 " sp=%016" PRIx64 "\n",
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++count, name, env->error_code, env->pc, env->ir[IR_SP]);
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}
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env->exception_index = -1;
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#if !defined(CONFIG_USER_ONLY)
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switch (i) {
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case EXCP_RESET:
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i = 0x0000;
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break;
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case EXCP_MCHK:
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i = 0x0080;
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break;
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case EXCP_SMP_INTERRUPT:
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i = 0x0100;
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break;
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case EXCP_CLK_INTERRUPT:
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i = 0x0180;
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break;
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case EXCP_DEV_INTERRUPT:
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i = 0x0200;
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break;
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case EXCP_MMFAULT:
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i = 0x0280;
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break;
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case EXCP_UNALIGN:
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i = 0x0300;
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break;
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case EXCP_OPCDEC:
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i = 0x0380;
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break;
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case EXCP_ARITH:
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i = 0x0400;
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break;
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case EXCP_FEN:
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i = 0x0480;
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break;
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case EXCP_CALL_PAL:
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i = env->error_code;
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/* There are 64 entry points for both privileged and unprivileged,
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with bit 0x80 indicating unprivileged. Each entry point gets
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64 bytes to do its job. */
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if (i & 0x80) {
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i = 0x2000 + (i - 0x80) * 64;
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} else {
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i = 0x1000 + i * 64;
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}
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break;
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default:
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cpu_abort(env, "Unhandled CPU exception");
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}
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/* Remember where the exception happened. Emulate real hardware in
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that the low bit of the PC indicates PALmode. */
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env->exc_addr = env->pc | env->pal_mode;
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/* Continue execution at the PALcode entry point. */
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env->pc = env->palbr + i;
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/* Switch to PALmode. */
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if (!env->pal_mode) {
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env->pal_mode = 1;
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swap_shadow_regs(env);
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}
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#endif /* !USER_ONLY */
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}
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void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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static const char *linux_reg_names[] = {
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"v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
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"t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
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"a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
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"t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
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};
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int i;
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cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
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env->pc, env->ps);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
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linux_reg_names[i], env->ir[i]);
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if ((i % 3) == 2)
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cpu_fprintf(f, "\n");
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}
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cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n",
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env->lock_addr, env->lock_value);
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for (i = 0; i < 31; i++) {
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cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i,
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*((uint64_t *)(&env->fir[i])));
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if ((i % 3) == 2)
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cpu_fprintf(f, "\n");
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}
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cpu_fprintf(f, "\n");
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}
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