cae323572e
We should only start processing DMA requests when we have data to process. Hold off working through the DMA shuffling until the IDE core told us that it's ready. This is required because the guest can program the DMA engine or the IDE transfer first. Both are legal. Signed-off-by: Alexander Graf <agraf@suse.de>
185 lines
5.0 KiB
C
185 lines
5.0 KiB
C
/*
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* QEMU PowerMac emulation shared definitions and prototypes
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if !defined(__PPC_MAC_H__)
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#define __PPC_MAC_H__
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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#include "hw/ide/internal.h"
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#include "hw/input/adb.h"
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define BIOS_SIZE (1024 * 1024)
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#define BIOS_FILENAME "ppc_rom.bin"
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#define NVRAM_SIZE 0x2000
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#define PROM_FILENAME "openbios-ppc"
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#define PROM_ADDR 0xfff00000
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#define KERNEL_LOAD_ADDR 0x01000000
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#define KERNEL_GAP 0x00100000
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#define ESCC_CLOCK 3686400
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/* Cuda */
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#define TYPE_CUDA "cuda"
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#define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA)
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/**
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* CUDATimer:
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* @counter_value: counter value at load time
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*/
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typedef struct CUDATimer {
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int index;
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uint16_t latch;
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uint16_t counter_value;
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int64_t load_time;
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int64_t next_irq_time;
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QEMUTimer *timer;
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} CUDATimer;
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/**
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* CUDAState:
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* @b: B-side data
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* @a: A-side data
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* @dirb: B-side direction (1=output)
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* @dira: A-side direction (1=output)
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* @sr: Shift register
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* @acr: Auxiliary control register
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* @pcr: Peripheral control register
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* @ifr: Interrupt flag register
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* @ier: Interrupt enable register
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* @anh: A-side data, no handshake
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* @last_b: last value of B register
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* @last_acr: last value of ACR register
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*/
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typedef struct CUDAState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mem;
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/* cuda registers */
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uint8_t b;
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uint8_t a;
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uint8_t dirb;
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uint8_t dira;
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uint8_t sr;
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uint8_t acr;
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uint8_t pcr;
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uint8_t ifr;
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uint8_t ier;
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uint8_t anh;
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ADBBusState adb_bus;
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CUDATimer timers[2];
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uint32_t tick_offset;
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uint8_t last_b;
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uint8_t last_acr;
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int data_in_size;
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int data_in_index;
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int data_out_index;
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qemu_irq irq;
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uint8_t autopoll;
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uint8_t data_in[128];
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uint8_t data_out[16];
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QEMUTimer *adb_poll_timer;
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} CUDAState;
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/* MacIO */
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#define TYPE_OLDWORLD_MACIO "macio-oldworld"
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#define TYPE_NEWWORLD_MACIO "macio-newworld"
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#define TYPE_MACIO_IDE "macio-ide"
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#define MACIO_IDE(obj) OBJECT_CHECK(MACIOIDEState, (obj), TYPE_MACIO_IDE)
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typedef struct MACIOIDEState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq irq;
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qemu_irq dma_irq;
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MemoryRegion mem;
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IDEBus bus;
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BlockDriverAIOCB *aiocb;
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IDEDMA dma;
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void *dbdma;
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bool dma_active;
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} MACIOIDEState;
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void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);
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void macio_ide_register_dma(MACIOIDEState *ide, void *dbdma, int channel);
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void macio_init(PCIDevice *dev,
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MemoryRegion *pic_mem,
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MemoryRegion *escc_mem);
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/* Heathrow PIC */
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qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
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int nb_cpus, qemu_irq **irqs);
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/* Grackle PCI */
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#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
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PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io);
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/* UniNorth PCI */
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PCIBus *pci_pmac_init(qemu_irq *pic,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io);
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PCIBus *pci_pmac_u3_init(qemu_irq *pic,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io);
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/* Mac NVRAM */
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#define TYPE_MACIO_NVRAM "macio-nvram"
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#define MACIO_NVRAM(obj) \
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OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM)
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typedef struct MacIONVRAMState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t size;
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uint32_t it_shift;
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MemoryRegion mem;
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uint8_t *data;
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} MacIONVRAMState;
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void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
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uint8_t macio_nvram_read(MacIONVRAMState *s, uint32_t addr);
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void macio_nvram_write(MacIONVRAMState *s, uint32_t addr, uint8_t val);
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#endif /* !defined(__PPC_MAC_H__) */
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