ecb0e98b4f
Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is disabled', but apparently MorphOS is using it in the version of the i8259 which is in the Pegasos2 board as part of the VT8231 chipset. It's easy enough to implement, and I think it's harmless enough to do so unconditionally. Signed-off-by: David Woodhouse <dwmw2@infradead.org> [balaton: updated commit message as asked by author] Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <3f09b2dd109d19851d786047ad5c2ff459c90cd7.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
78 lines
2.6 KiB
C
78 lines
2.6 KiB
C
/*
|
|
* QEMU 8259 - internal interfaces
|
|
*
|
|
* Copyright (c) 2011 Jan Kiszka, Siemens AG
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
* in the Software without restriction, including without limitation the rights
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
* furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
* THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef QEMU_I8259_INTERNAL_H
|
|
#define QEMU_I8259_INTERNAL_H
|
|
|
|
#include "hw/isa/isa.h"
|
|
#include "hw/intc/intc.h"
|
|
#include "hw/intc/i8259.h"
|
|
#include "qom/object.h"
|
|
|
|
|
|
#define TYPE_PIC_COMMON "pic-common"
|
|
OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, PIC_COMMON)
|
|
|
|
struct PICCommonClass {
|
|
DeviceClass parent_class;
|
|
|
|
void (*pre_save)(PICCommonState *s);
|
|
void (*post_load)(PICCommonState *s);
|
|
};
|
|
|
|
struct PICCommonState {
|
|
ISADevice parent_obj;
|
|
|
|
uint8_t last_irr; /* edge detection */
|
|
uint8_t irr; /* interrupt request register */
|
|
uint8_t imr; /* interrupt mask register */
|
|
uint8_t isr; /* interrupt service register */
|
|
uint8_t priority_add; /* highest irq priority */
|
|
uint8_t irq_base;
|
|
uint8_t read_reg_select;
|
|
uint8_t poll;
|
|
uint8_t special_mask;
|
|
uint8_t init_state;
|
|
uint8_t auto_eoi;
|
|
uint8_t rotate_on_auto_eoi;
|
|
uint8_t special_fully_nested_mode;
|
|
uint8_t init4; /* true if 4 byte init */
|
|
uint8_t single_mode; /* true if slave pic is not initialized */
|
|
uint8_t elcr; /* PIIX edge/trigger selection*/
|
|
uint8_t elcr_mask;
|
|
uint8_t ltim; /* Edge/Level Bank Select (pre-PIIX, chip-wide) */
|
|
qemu_irq int_out[1];
|
|
uint32_t master; /* reflects /SP input pin */
|
|
uint32_t iobase;
|
|
uint32_t elcr_addr;
|
|
MemoryRegion base_io;
|
|
MemoryRegion elcr_io;
|
|
};
|
|
|
|
void pic_reset_common(PICCommonState *s);
|
|
ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master);
|
|
void pic_stat_update_irq(int irq, int level);
|
|
|
|
#endif /* QEMU_I8259_INTERNAL_H */
|