qemu/include
Peter Maydell 2ac031d171 RISC-V Patches for the 5.0 Soft Freeze, Part 3
This pull request is almost entirely an implementation of the draft hypervisor
 extension.  This extension is still in draft and is expected to have
 incompatible changes before being frozen, but we've had good luck managing
 other RISC-V draft extensions in QEMU so far.
 
 Additionally, there's a fix to PCI addressing and some improvements to the
 M-mode timer.
 
 This boots linux and passes make check for me.
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' into staging

RISC-V Patches for the 5.0 Soft Freeze, Part 3

This pull request is almost entirely an implementation of the draft hypervisor
extension.  This extension is still in draft and is expected to have
incompatible changes before being frozen, but we've had good luck managing
other RISC-V draft extensions in QEMU so far.

Additionally, there's a fix to PCI addressing and some improvements to the
M-mode timer.

This boots linux and passes make check for me.

# gpg: Signature made Tue 03 Mar 2020 00:23:20 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf3: (38 commits)
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation
  target/riscv: Emulate TIME CSRs for privileged mode
  riscv: virt: Allow PCI address 0
  target/riscv: Allow enabling the Hypervisor extension
  target/riscv: Add the MSTATUS_MPV_ISSET helper macro
  target/riscv: Add support for the 32-bit MSTATUSH CSR
  target/riscv: Set htval and mtval2 on execptions
  target/riscv: Raise the new execptions when 2nd stage translation fails
  target/riscv: Implement second stage MMU
  target/riscv: Allow specifying MMU stage
  target/riscv: Respect MPRV and SPRV for floating point ops
  target/riscv: Mark both sstatus and msstatus_hs as dirty
  target/riscv: Disable guest FP support based on virtual status
  target/riscv: Only set TB flags with FP status if enabled
  target/riscv: Remove the hret instruction
  target/riscv: Add hfence instructions
  target/riscv: Add Hypervisor trap return support
  target/riscv: Add hypvervisor trap support
  target/riscv: Generate illegal instruction on WFI when V=1
  target/ricsv: Flush the TLB on virtulisation mode changes
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-03-03 11:06:39 +00:00
..
authz Include generated QAPI headers less 2019-08-16 13:31:51 +02:00
block aio-posix: make AioHandler deletion O(1) 2020-02-22 08:26:47 +00:00
chardev chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
crypto crypto: Fix typo in QCryptoTLSSession's <example> comment 2019-12-18 08:36:15 +01:00
disas disas: Add a field for target-dependant data to disassemble_info 2020-01-29 19:28:52 +01:00
exec Let cpu_[physical]_memory() calls pass a boolean 'is_write' argument 2020-02-20 14:47:08 +01:00
fpu fpu: make softfloat-macros "self-contained" 2019-08-19 12:07:13 +01:00
hw RISC-V Patches for the 5.0 Soft Freeze, Part 3 2020-03-03 11:06:39 +00:00
io io: Fix Error usage in a comment <example> 2019-12-18 08:36:15 +01:00
libdecnumber include: Make headers more self-contained 2019-08-16 13:31:51 +02:00
migration migration: Support QLIST migration 2020-01-20 09:10:23 +01:00
monitor monitor: Move monitor option parsing to monitor/monitor.c 2020-02-17 13:47:48 +01:00
net Include qemu/queue.h slightly less 2019-08-16 13:31:52 +02:00
qapi qstring: add qstring_free() 2020-01-24 20:59:13 +01:00
qemu compiler.h: Don't use compile-time assert when __NO_INLINE__ is defined 2020-02-28 10:58:41 -08:00
qom qom: introduce object_property_help() 2020-01-24 20:59:16 +01:00
scsi scsi: explicitly list guest-recoverable sense codes 2019-07-15 11:20:42 +02:00
standard-headers linux-headers: update 2020-02-26 18:57:07 +01:00
sysemu Merge tag 'patchew/20200219160953.13771-1-imammedo@redhat.com' of https://github.com/patchew-project/qemu into HEAD 2020-02-25 09:19:00 +01:00
tcg tcg: Add tcg_gen_gvec_5_ptr 2020-02-12 14:58:36 -08:00
ui display/gtk: get proper refreshrate 2020-01-14 07:26:36 +01:00
user linux-user: Include trace-root.h in syscall-trace.h 2020-01-15 15:13:09 -10:00
elf.h target/arm/arch_dump: Add SVE notes 2020-01-23 15:34:04 +00:00
glib-compat.h glib: bump min required glib library version to 2.48 2019-08-22 10:46:34 +01:00
qemu-common.h exec: Split out variable page size support to exec-vary.c 2019-10-28 10:26:02 +01:00
qemu-io.h Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
trace-tcg.h