3a0f31bcb8
The sabrelite supports one SPI FLASH memory on SPI1 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
122 lines
3.9 KiB
C
122 lines
3.9 KiB
C
/*
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* SABRELITE Board System emulation.
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*
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* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This code is licensed under the GPL, version 2 or later.
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* See the file `COPYING' in the top level directory.
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*
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* It (partially) emulates a sabrelite board, with a Freescale
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* i.MX6 SoC
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/arm/fsl-imx6.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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#include "qemu/error-report.h"
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#include "sysemu/qtest.h"
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typedef struct IMX6Sabrelite {
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FslIMX6State soc;
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MemoryRegion ram;
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} IMX6Sabrelite;
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static struct arm_boot_info sabrelite_binfo = {
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/* DDR memory start */
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.loader_start = FSL_IMX6_MMDC_ADDR,
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/* No board ID, we boot from DT tree */
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.board_id = -1,
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};
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/* No need to do any particular setup for secondary boot */
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static void sabrelite_write_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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}
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/* Secondary cores are reset through SRC device */
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static void sabrelite_reset_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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}
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static void sabrelite_init(MachineState *machine)
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{
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IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1);
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Error *err = NULL;
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/* Check the amount of memory is compatible with the SOC */
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if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
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error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
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machine->ram_size, FSL_IMX6_MMDC_SIZE);
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exit(1);
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}
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object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX6);
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object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
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&error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
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if (err != NULL) {
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error_report("%s", error_get_pretty(err));
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exit(1);
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}
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memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram",
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machine->ram_size);
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memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
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&s->ram);
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{
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/*
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* TODO: Ideally we would expose the chip select and spi bus on the
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* SoC object using alias properties; then we would not need to
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* directly access the underlying spi device object.
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*/
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/* Add the sst25vf016b NOR FLASH memory to first SPI */
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Object *spi_dev;
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spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
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if (spi_dev) {
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SSIBus *spi_bus;
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spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
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if (spi_bus) {
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DeviceState *flash_dev;
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flash_dev = ssi_create_slave(spi_bus, "sst25vf016b");
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if (flash_dev) {
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qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev,
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SSI_GPIO_CS, 0);
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sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
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}
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}
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}
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}
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sabrelite_binfo.ram_size = machine->ram_size;
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sabrelite_binfo.kernel_filename = machine->kernel_filename;
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sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline;
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sabrelite_binfo.initrd_filename = machine->initrd_filename;
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sabrelite_binfo.nb_cpus = smp_cpus;
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sabrelite_binfo.secure_boot = true;
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sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
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sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
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if (!qtest_enabled()) {
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arm_load_kernel(&s->soc.cpu[0], &sabrelite_binfo);
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}
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}
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static void sabrelite_machine_init(MachineClass *mc)
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{
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mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
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mc->init = sabrelite_init;
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mc->max_cpus = FSL_IMX6_NUM_CPUS;
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}
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DEFINE_MACHINE("sabrelite", sabrelite_machine_init)
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