5204ea79ea
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> |
||
|---|---|---|
| .. | ||
| libvixl | ||
| alpha.c | ||
| arm-a64.cc | ||
| arm.c | ||
| cris.c | ||
| hppa.c | ||
| i386.c | ||
| ia64.c | ||
| lm32.c | ||
| m68k.c | ||
| Makefile.objs | ||
| microblaze.c | ||
| mips.c | ||
| moxie.c | ||
| ppc.c | ||
| s390.c | ||
| sh4.c | ||
| sparc.c | ||
| tci.c | ||