2419978cb0
We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Rui Wang <wangrui@loongson.cn> Message-Id: <20221104040517.222059-3-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
64 lines
1.5 KiB
C++
64 lines
1.5 KiB
C++
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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/* bit0(signaling/quiet) bit1(lt) bit2(eq) bit3(un) bit4(neq) */
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static uint32_t get_fcmp_flags(int cond)
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{
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uint32_t flags = 0;
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if (cond & 0x1) {
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flags |= FCMP_LT;
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}
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if (cond & 0x2) {
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flags |= FCMP_EQ;
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}
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if (cond & 0x4) {
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flags |= FCMP_UN;
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}
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if (cond & 0x8) {
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flags |= FCMP_GT | FCMP_LT;
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}
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return flags;
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}
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static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
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{
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TCGv var;
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uint32_t flags;
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void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
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CHECK_FPE;
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var = tcg_temp_new();
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fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
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flags = get_fcmp_flags(a->fcond >> 1);
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fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
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tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
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tcg_temp_free(var);
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return true;
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}
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static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
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{
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TCGv var;
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uint32_t flags;
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void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
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CHECK_FPE;
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var = tcg_temp_new();
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fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
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flags = get_fcmp_flags(a->fcond >> 1);
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fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
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tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
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tcg_temp_free(var);
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return true;
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}
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