qemu/hw/riscv
Bin Meng 5474aa4f3e hw/riscv: virt: Simplify virt_{get,set}_aclint()
There is no need to declare an intermediate "MachineState *ms".

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230206085007.3618715-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07 08:21:32 +10:00
..
boot.c hw/riscv: change riscv_compute_fdt_addr() semantics 2023-02-07 08:19:23 +10:00
Kconfig hw/riscv: Sort machines Kconfig options in alphabetical order 2023-01-06 10:42:55 +10:00
meson.build hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines 2021-07-20 15:32:49 +02:00
microchip_pfsoc.c hw/riscv: change riscv_compute_fdt_addr() semantics 2023-02-07 08:19:23 +10:00
numa.c hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() 2023-01-20 10:14:14 +10:00
opentitan.c include/hw/riscv/opentitan: update opentitan IRQs 2023-02-07 08:19:22 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() 2022-09-07 09:18:33 +02:00
sifive_e.c hw/riscv/boot.c: use MachineState in riscv_load_kernel() 2023-01-20 10:14:13 +10:00
sifive_u.c hw/riscv: change riscv_compute_fdt_addr() semantics 2023-02-07 08:19:23 +10:00
spike.c hw/riscv: change riscv_compute_fdt_addr() semantics 2023-02-07 08:19:23 +10:00
virt.c hw/riscv: virt: Simplify virt_{get,set}_aclint() 2023-02-07 08:21:32 +10:00