91e3c43722
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230306175230.7110-8-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
34 lines
885 B
C
34 lines
885 B
C
/*
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* PA-RISC cpu parameters for qemu.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef HPPA_CPU_PARAM_H
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#define HPPA_CPU_PARAM_H
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#ifdef TARGET_HPPA64
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# define TARGET_LONG_BITS 64
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# define TARGET_REGISTER_BITS 64
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# define TARGET_VIRT_ADDR_SPACE_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 64
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#elif defined(CONFIG_USER_ONLY)
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# define TARGET_LONG_BITS 32
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# define TARGET_REGISTER_BITS 32
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 32
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#else
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/*
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* In order to form the GVA from space:offset,
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* we need a 64-bit virtual address space.
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*/
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# define TARGET_LONG_BITS 64
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# define TARGET_REGISTER_BITS 32
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# define TARGET_VIRT_ADDR_SPACE_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 32
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#endif
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#define TARGET_PAGE_BITS 12
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#endif
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