4e88e7e340
The x86 and ARM need to allow user to configure cache properties
(current only topology):
* For x86, the default cache topology model (of max/host CPU) does not
always match the Host's real physical cache topology. Performance can
increase when the configured virtual topology is closer to the
physical topology than a default topology would be.
* For ARM, QEMU can't get the cache topology information from the CPU
registers, then user configuration is necessary. Additionally, the
cache information is also needed for MPAM emulation (for TCG) to
build the right PPTT.
Define smp-cache related enumeration and properties in QAPI, so that
user could configure cache properties for SMP system through -machine in
the subsequent patch.
Cache enumeration (CacheLevelAndType) is implemented as the combination
of cache level (level 1/2/3) and cache type (data/instruction/unified).
Currently, separated L1 cache (L1 data cache and L1 instruction cache)
with unified higher-level cache (e.g., unified L2 and L3 caches), is the
most common cache architectures.
Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache
with smp-cache object to add the basic cache topology support. Other
kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be
added directly into CacheLevelAndType if necessary.
Cache properties (SmpCacheProperties) currently only contains cache
topology information, and other cache properties can be added in it
if necessary.
Note, define cache topology based on CPU topology level with two
reasons:
1. In practice, a cache will always be bound to the CPU container
(either private in the CPU container or shared among multiple
containers), and CPU container is often expressed in terms of CPU
topology level.
2. The x86's cache-related CPUIDs encode cache topology based on APIC
ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV
relies on also requires CPU containers to help indicate the private
shared hierarchy of the cache. Therefore, for SMP systems, it is
natural to use the CPU topology hierarchy directly in QEMU to define
the cache topology.
With smp-cache QAPI support, add smp cache topology for machine by
parsing the smp-cache object list.
Also add the helper to access/update cache topology level of machine.
Suggested-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-ID: <20241101083331.340178-4-zhao1.liu@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
113 lines
2.9 KiB
Python
113 lines
2.9 KiB
Python
# -*- Mode: Python -*-
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# vim: filetype=python
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#
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# This work is licensed under the terms of the GNU GPL, version 2 or later.
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# See the COPYING file in the top-level directory.
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##
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# = Common machine types
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##
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##
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# @S390CpuEntitlement:
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#
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# An enumeration of CPU entitlements that can be assumed by a virtual
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# S390 CPU
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#
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# Since: 8.2
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##
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{ 'enum': 'S390CpuEntitlement',
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'data': [ 'auto', 'low', 'medium', 'high' ] }
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##
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# @CpuTopologyLevel:
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#
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# An enumeration of CPU topology levels.
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#
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# @thread: thread level, which would also be called SMT level or
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# logical processor level. The @threads option in
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# SMPConfiguration is used to configure the topology of this
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# level.
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#
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# @core: core level. The @cores option in SMPConfiguration is used
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# to configure the topology of this level.
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#
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# @module: module level. The @modules option in SMPConfiguration is
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# used to configure the topology of this level.
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#
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# @cluster: cluster level. The @clusters option in SMPConfiguration
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# is used to configure the topology of this level.
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#
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# @die: die level. The @dies option in SMPConfiguration is used to
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# configure the topology of this level.
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#
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# @socket: socket level, which would also be called package level.
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# The @sockets option in SMPConfiguration is used to configure
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# the topology of this level.
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#
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# @book: book level. The @books option in SMPConfiguration is used
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# to configure the topology of this level.
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#
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# @drawer: drawer level. The @drawers option in SMPConfiguration is
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# used to configure the topology of this level.
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#
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# @default: default level. Some architectures will have default
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# topology settings (e.g., cache topology), and this special
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# level means following the architecture-specific settings.
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#
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# Since: 9.2
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##
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{ 'enum': 'CpuTopologyLevel',
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'data': [ 'thread', 'core', 'module', 'cluster', 'die',
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'socket', 'book', 'drawer', 'default' ] }
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##
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# @CacheLevelAndType:
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#
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# Caches a system may have. The enumeration value here is the
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# combination of cache level and cache type.
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#
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# @l1d: L1 data cache.
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#
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# @l1i: L1 instruction cache.
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#
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# @l2: L2 (unified) cache.
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#
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# @l3: L3 (unified) cache
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#
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# Since: 9.2
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##
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{ 'enum': 'CacheLevelAndType',
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'data': [ 'l1d', 'l1i', 'l2', 'l3' ] }
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##
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# @SmpCacheProperties:
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#
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# Cache information for SMP system.
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#
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# @cache: Cache name, which is the combination of cache level
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# and cache type.
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#
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# @topology: Cache topology level. It accepts the CPU topology
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# enumeration as the parameter, i.e., CPUs in the same
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# topology container share the same cache.
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#
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# Since: 9.2
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##
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{ 'struct': 'SmpCacheProperties',
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'data': {
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'cache': 'CacheLevelAndType',
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'topology': 'CpuTopologyLevel' } }
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##
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# @SmpCachePropertiesWrapper:
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#
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# List wrapper of SmpCacheProperties.
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#
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# @caches: the list of SmpCacheProperties.
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#
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# Since 9.2
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##
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{ 'struct': 'SmpCachePropertiesWrapper',
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'data': { 'caches': ['SmpCacheProperties'] } }
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