ef17dd6a8e
Update headers to 5.17-rc1. I need latest fuse changes. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20220208204813.682906-3-vgoyal@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
66 lines
2.4 KiB
C
66 lines
2.4 KiB
C
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
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/*
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* Copyright (C) 2021 Intel Corporation
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* Author: Johannes Berg <johannes@sipsolutions.net>
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*/
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#ifndef _LINUX_VIRTIO_PCIDEV_H
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#define _LINUX_VIRTIO_PCIDEV_H
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#include "standard-headers/linux/types.h"
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/**
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* enum virtio_pcidev_ops - virtual PCI device operations
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* @VIRTIO_PCIDEV_OP_RESERVED: reserved to catch errors
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* @VIRTIO_PCIDEV_OP_CFG_READ: read config space, size is 1, 2, 4 or 8;
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* the @data field should be filled in by the device (in little endian).
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* @VIRTIO_PCIDEV_OP_CFG_WRITE: write config space, size is 1, 2, 4 or 8;
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* the @data field contains the data to write (in little endian).
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* @VIRTIO_PCIDEV_OP_MMIO_READ: read BAR mem/pio, size can be variable;
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* the @data field should be filled in by the device (in little endian).
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* @VIRTIO_PCIDEV_OP_MMIO_WRITE: write BAR mem/pio, size can be variable;
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* the @data field contains the data to write (in little endian).
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* @VIRTIO_PCIDEV_OP_MMIO_MEMSET: memset MMIO, size is variable but
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* the @data field only has one byte (unlike @VIRTIO_PCIDEV_OP_MMIO_WRITE)
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* @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for
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* the number
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* @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports
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* the 16- or 32-bit write that would otherwise be done into memory,
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* analogous to the write messages (@VIRTIO_PCIDEV_OP_MMIO_WRITE) above
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* @VIRTIO_PCIDEV_OP_PME: Dummy message whose content is ignored (and should be
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* all zeroes) to signal the PME# pin.
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*/
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enum virtio_pcidev_ops {
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VIRTIO_PCIDEV_OP_RESERVED = 0,
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VIRTIO_PCIDEV_OP_CFG_READ,
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VIRTIO_PCIDEV_OP_CFG_WRITE,
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VIRTIO_PCIDEV_OP_MMIO_READ,
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VIRTIO_PCIDEV_OP_MMIO_WRITE,
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VIRTIO_PCIDEV_OP_MMIO_MEMSET,
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VIRTIO_PCIDEV_OP_INT,
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VIRTIO_PCIDEV_OP_MSI,
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VIRTIO_PCIDEV_OP_PME,
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};
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/**
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* struct virtio_pcidev_msg - virtio PCI device operation
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* @op: the operation to do
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* @bar: the bar (only with BAR read/write messages)
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* @reserved: reserved
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* @size: the size of the read/write (in bytes)
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* @addr: the address to read/write
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* @data: the data, normally @size long, but just one byte for
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* %VIRTIO_PCIDEV_OP_MMIO_MEMSET
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*
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* Note: the fields are all in native (CPU) endian, however, the
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* @data values will often be in little endian (see the ops above.)
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*/
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struct virtio_pcidev_msg {
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uint8_t op;
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uint8_t bar;
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uint16_t reserved;
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uint32_t size;
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uint64_t addr;
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uint8_t data[];
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};
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#endif /* _LINUX_VIRTIO_PCIDEV_H */
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