Philippe Mathieu-Daudé 17b3c353e6 target/riscv: Restrict cpu_exec_interrupt() handler to sysemu ...

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210911165434.531552-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2021-09-14 12:00:21 -07:00

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insn_trans

target/riscv: Use {get,dest}_gpr for RVV

2021-09-01 11:59:12 +10:00

arch_dump.c

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bitmanip_helper.c

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cpu_bits.h

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cpu_helper.c

target/riscv: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-14 12:00:21 -07:00

cpu_user.h

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cpu-param.h

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cpu.c

target/riscv: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-14 12:00:21 -07:00

cpu.h

target/riscv: Restrict cpu_exec_interrupt() handler to sysemu

2021-09-14 12:00:21 -07:00

csr.c

target/riscv: Fix hgeie, hgeip

2021-09-01 11:59:12 +10:00

fpu_helper.c

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gdbstub.c

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helper.h

target/riscv: Reorg csr instructions

2021-09-01 11:59:12 +10:00

insn16.decode

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insn32.decode

target/riscv: Tidy trans_rvh.c.inc

2021-09-01 11:59:12 +10:00

instmap.h

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internals.h

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Kconfig

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machine.c

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meson.build

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monitor.c

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op_helper.c

target/riscv: Reorg csr instructions

2021-09-01 11:59:12 +10:00

pmp.c

target/riscv: pmp: Fix some typos

2021-07-15 08:56:00 +10:00

pmp.h

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trace-events

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trace.h

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translate.c

accel/tcg: Add DisasContextBase argument to translator_ld*

2021-09-14 12:00:20 -07:00

vector_helper.c

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