qemu/hw/riscv/Kconfig
Thomas Huth 259181d29f hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device
The cpu-cluster device is only needed for some few arm and riscv
machines. Let's avoid compiling and linking it if it is not really
necessary.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240415065655.130099-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-04-25 12:48:12 +02:00

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config RISCV_NUMA
bool
config IBEX
bool
# RISC-V machines in alphabetical order
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
select CPU_CLUSTER
select MCHP_PFSOC_DMC
select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
select MCHP_PFSOC_SYSREG
select RISCV_ACLINT
select SIFIVE_PDMA
select SIFIVE_PLIC
select UNIMP
config OPENTITAN
bool
select IBEX
select SIFIVE_PLIC
select UNIMP
config RISCV_VIRT
bool
imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
imply TPM_TIS_SYSBUS
select RISCV_NUMA
select GOLDFISH_RTC
select PCI
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
select SERIAL
select RISCV_ACLINT
select RISCV_APLIC
select RISCV_IMSIC
select SIFIVE_PLIC
select SIFIVE_TEST
select SMBIOS
select VIRTIO_MMIO
select FW_CFG_DMA
select PLATFORM_BUS
select ACPI
select ACPI_PCI
config SHAKTI_C
bool
select RISCV_ACLINT
select SHAKTI_UART
select SIFIVE_PLIC
select UNIMP
config SIFIVE_E
bool
select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
select SIFIVE_UART
select SIFIVE_E_PRCI
select SIFIVE_E_AON
select UNIMP
config SIFIVE_U
bool
select CADENCE
select CPU_CLUSTER
select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_PLIC
select SIFIVE_SPI
select SIFIVE_UART
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
select SIFIVE_PWM
select SSI_M25P80
select SSI_SD
select UNIMP
config SPIKE
bool
select RISCV_NUMA
select HTIF
select RISCV_ACLINT
select SIFIVE_PLIC