781c67ca55
The CPUClass has a 'reset' method. This is a legacy from when TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()' function is kept as the API which most places use to reset a CPU; it is now a wrapper which calls device_cold_reset() and then the tracepoint function. This change should not cause CPU objects to be reset more often than they are at the moment, because: * nobody is directly calling device_cold_reset() or qdev_reset_all() on CPU objects * no CPU object is on a qbus, so they will not be reset either by somebody calling qbus_reset_all()/bus_cold_reset(), or by the main "reset sysbus and everything in the qbus tree" reset that most devices are reset by Note that this does not change the need for each machine or whatever to use qemu_register_reset() to arrange to call cpu_reset() -- that is necessary because CPU objects are not on any qbus, so they don't get reset when the qbus tree rooted at the sysbus bus is reset, and this isn't being changed here. All the changes to the files under target/ were made using the included Coccinelle script, except: (1) the deletion of the now-inaccurate and not terribly useful "CPUClass::reset" comments was done with a perl one-liner afterwards: perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c (2) this bit of the s390 change was done by hand, because the Coccinelle script is not sophisticated enough to handle the parent_reset call being inside another function: | @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | S390CPU *cpu = S390_CPU(s); | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | CPUS390XState *env = &cpu->env; |+ DeviceState *dev = DEVICE(s); | |- scc->parent_reset(s); |+ scc->parent_reset(dev); | cpu->env.sigp_order = 0; | s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_ARM_CPU_QOM_H
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#define QEMU_ARM_CPU_QOM_H
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#include "hw/core/cpu.h"
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struct arm_boot_info;
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#define TYPE_ARM_CPU "arm-cpu"
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#define ARM_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
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#define ARM_CPU(obj) \
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OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
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#define ARM_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
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#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
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typedef struct ARMCPUInfo ARMCPUInfo;
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/**
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* ARMCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* An ARM CPU model.
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*/
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typedef struct ARMCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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const ARMCPUInfo *info;
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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} ARMCPUClass;
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typedef struct ARMCPU ARMCPU;
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#define TYPE_AARCH64_CPU "aarch64-cpu"
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#define AARCH64_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
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#define AARCH64_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
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typedef struct AArch64CPUClass {
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/*< private >*/
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ARMCPUClass parent_class;
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/*< public >*/
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} AArch64CPUClass;
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void register_cp_regs_for_features(ARMCPU *cpu);
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void init_cpreg_list(ARMCPU *cpu);
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/* Callback functions for the generic timer's timers. */
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void arm_gt_ptimer_cb(void *opaque);
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void arm_gt_vtimer_cb(void *opaque);
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void arm_gt_htimer_cb(void *opaque);
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void arm_gt_stimer_cb(void *opaque);
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void arm_gt_hvtimer_cb(void *opaque);
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#define ARM_AFF0_SHIFT 0
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#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
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#define ARM_AFF1_SHIFT 8
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#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
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#define ARM_AFF2_SHIFT 16
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#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
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#define ARM_AFF3_SHIFT 32
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#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
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#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
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#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
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#define ARM64_AFFINITY_MASK \
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(ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
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#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
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#endif
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