69d9c74fa9
This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-36-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
199 lines
6.6 KiB
C
199 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU loongson 3a5000 develop board emulation
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/datadir.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "sysemu/runstate.h"
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#include "sysemu/reset.h"
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#include "sysemu/rtc.h"
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#include "hw/loongarch/virt.h"
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#include "exec/address-spaces.h"
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#include "hw/intc/loongarch_ipi.h"
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#include "hw/intc/loongarch_extioi.h"
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#include "hw/intc/loongarch_pch_pic.h"
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#include "hw/intc/loongarch_pch_msi.h"
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#include "hw/pci-host/ls7a.h"
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#include "target/loongarch/cpu.h"
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static void loongarch_irq_init(LoongArchMachineState *lams)
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{
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MachineState *ms = MACHINE(lams);
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DeviceState *pch_pic, *pch_msi, *cpudev;
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DeviceState *ipi, *extioi;
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SysBusDevice *d;
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LoongArchCPU *lacpu;
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CPULoongArchState *env;
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CPUState *cpu_state;
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int cpu, pin, i;
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ipi = qdev_new(TYPE_LOONGARCH_IPI);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
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extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
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/*
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* The connection of interrupts:
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* +-----+ +---------+ +-------+
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* | IPI |--> | CPUINTC | <-- | Timer |
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* +-----+ +---------+ +-------+
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* ^
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* |
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* +---------+
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* | EIOINTC |
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* +---------+
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* ^ ^
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* | |
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* +---------+ +---------+
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* | PCH-PIC | | PCH-MSI |
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* +---------+ +---------+
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* ^ ^ ^
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* | | |
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* +--------+ +---------+ +---------+
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* | UARTs | | Devices | | Devices |
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* +--------+ +---------+ +---------+
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*/
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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cpu_state = qemu_get_cpu(cpu);
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cpudev = DEVICE(cpu_state);
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lacpu = LOONGARCH_CPU(cpu_state);
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env = &(lacpu->env);
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/* connect ipi irq to cpu irq */
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qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
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/* IPI iocsr memory region */
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memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
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cpu));
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/* extioi iocsr memory region */
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memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
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cpu));
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}
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/*
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* connect ext irq to the cpu irq
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* cpu_pin[9:2] <= intc_pin[7:0]
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*/
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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cpudev = DEVICE(qemu_get_cpu(cpu));
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for (pin = 0; pin < LS3A_INTC_IP; pin++) {
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qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
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qdev_get_gpio_in(cpudev, pin + 2));
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}
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}
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pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
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d = SYS_BUS_DEVICE(pch_pic);
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sysbus_realize_and_unref(d, &error_fatal);
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memory_region_add_subregion(get_system_memory(), LS7A_IOAPIC_REG_BASE,
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sysbus_mmio_get_region(d, 0));
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memory_region_add_subregion(get_system_memory(),
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LS7A_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
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sysbus_mmio_get_region(d, 1));
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memory_region_add_subregion(get_system_memory(),
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LS7A_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
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sysbus_mmio_get_region(d, 2));
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/* Connect 64 pch_pic irqs to extioi */
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for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
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qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
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}
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pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
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d = SYS_BUS_DEVICE(pch_msi);
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sysbus_realize_and_unref(d, &error_fatal);
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sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW);
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for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
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/* Connect 192 pch_msi irqs to extioi */
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qdev_connect_gpio_out(DEVICE(d), i,
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qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
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}
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}
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static void loongarch_init(MachineState *machine)
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{
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const char *cpu_model = machine->cpu_type;
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ram_addr_t offset = 0;
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ram_addr_t ram_size = machine->ram_size;
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uint64_t highram_size = 0;
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MemoryRegion *address_space_mem = get_system_memory();
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LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
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int i;
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if (!cpu_model) {
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cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
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}
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if (!strstr(cpu_model, "la464")) {
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error_report("LoongArch/TCG needs cpu type la464");
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exit(1);
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}
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if (ram_size < 1 * GiB) {
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error_report("ram_size must be greater than 1G.");
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exit(1);
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}
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/* Init CPUs */
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for (i = 0; i < machine->smp.cpus; i++) {
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cpu_create(machine->cpu_type);
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}
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/* Add memory region */
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memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
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machine->ram, 0, 256 * MiB);
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memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
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offset += 256 * MiB;
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highram_size = ram_size - 256 * MiB;
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memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
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machine->ram, offset, highram_size);
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memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
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/* Add isa io region */
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memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
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get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
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memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
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&lams->isa_io);
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/* Initialize the IO interrupt subsystem */
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loongarch_irq_init(lams);
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}
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static void loongarch_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "Loongson-3A5000 LS7A1000 machine";
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mc->init = loongarch_init;
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mc->default_ram_size = 1 * GiB;
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mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
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mc->default_ram_id = "loongarch.ram";
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mc->max_cpus = LOONGARCH_MAX_VCPUS;
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mc->is_default = 1;
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mc->default_kernel_irqchip_split = false;
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mc->block_default_type = IF_VIRTIO;
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mc->default_boot_order = "c";
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mc->no_cdrom = 1;
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}
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static const TypeInfo loongarch_machine_types[] = {
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{
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.name = TYPE_LOONGARCH_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(LoongArchMachineState),
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.class_init = loongarch_class_init,
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}
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};
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DEFINE_TYPES(loongarch_machine_types)
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