24db877ab6
Uses the existing gpex device which is also used as pcie host bridge on arm/aarch64. For now only a 32bit mmio window and no ioport support. It is disabled by default, use "-machine microvm,pcie=on" to enable. ACPI support must be enabled too because the bus is declared in the DSDT table. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200928104256.9241-6-kraxel@redhat.com
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2019 Red Hat, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_I386_MICROVM_H
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#define HW_I386_MICROVM_H
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#include "qemu-common.h"
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#include "exec/hwaddr.h"
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#include "qemu/notify.h"
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#include "hw/boards.h"
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#include "hw/i386/x86.h"
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#include "hw/acpi/acpi_dev_interface.h"
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#include "hw/pci-host/gpex.h"
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#include "qom/object.h"
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/*
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* IRQ | pc | microvm (acpi=on)
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* --------+------------+------------------
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* 0 | pit |
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* 1 | kbd |
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* 2 | cascade |
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* 3 | serial 1 |
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* 4 | serial 0 | serial
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* 5 | - |
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* 6 | floppy |
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* 7 | parallel |
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* 8 | rtc | rtc (rtc=on)
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* 9 | acpi | acpi (ged)
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* 10 | pci lnk |
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* 11 | pci lnk |
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* 12 | ps2 | pcie
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* 13 | fpu | pcie
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* 14 | ide 0 | pcie
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* 15 | ide 1 | pcie
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* 16-23 | pci gsi | virtio
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*/
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/* Platform virtio definitions */
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#define VIRTIO_MMIO_BASE 0xfeb00000
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#define VIRTIO_NUM_TRANSPORTS 8
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#define VIRTIO_CMDLINE_MAXLEN 64
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#define GED_MMIO_BASE 0xfea00000
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#define GED_MMIO_BASE_MEMHP (GED_MMIO_BASE + 0x100)
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#define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
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#define GED_MMIO_IRQ 9
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#define PCIE_MMIO_BASE 0xc0000000
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#define PCIE_MMIO_SIZE 0x20000000
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#define PCIE_ECAM_BASE 0xe0000000
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#define PCIE_ECAM_SIZE 0x10000000
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#define PCIE_IRQ_BASE 12
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/* Machine type options */
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#define MICROVM_MACHINE_PIT "pit"
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#define MICROVM_MACHINE_PIC "pic"
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#define MICROVM_MACHINE_RTC "rtc"
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#define MICROVM_MACHINE_PCIE "pcie"
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#define MICROVM_MACHINE_ISA_SERIAL "isa-serial"
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#define MICROVM_MACHINE_OPTION_ROMS "x-option-roms"
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#define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline"
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struct MicrovmMachineClass {
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X86MachineClass parent;
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HotplugHandler *(*orig_hotplug_handler)(MachineState *machine,
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DeviceState *dev);
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};
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struct MicrovmMachineState {
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X86MachineState parent;
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/* Machine type options */
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OnOffAuto pic;
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OnOffAuto pit;
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OnOffAuto rtc;
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OnOffAuto pcie;
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bool isa_serial;
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bool option_roms;
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bool auto_kernel_cmdline;
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/* Machine state */
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uint32_t virtio_irq_base;
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bool kernel_cmdline_fixed;
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Notifier machine_done;
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Notifier powerdown_req;
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struct GPEXConfig gpex;
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};
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#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
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OBJECT_DECLARE_TYPE(MicrovmMachineState, MicrovmMachineClass, MICROVM_MACHINE)
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#endif
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