24ce762df7
Our device have 2 different I/O regions:
- a 16550 UART mapped for 32-bit accesses
- 13 extra registers
Instead of mapping each region on the main bus, introduce
a container, map the 2 devices regions on the container,
and map the container on the main bus.
Before:
(qemu) info mtree
...
0000000020100000-000000002010001f (prio 0, i/o): serial
0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
0000000020102000-000000002010201f (prio 0, i/o): serial
0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
0000000020104000-000000002010401f (prio 0, i/o): serial
0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
0000000020106000-000000002010601f (prio 0, i/o): serial
0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart
After:
(qemu) info mtree
...
0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020100000-000000002010001f (prio 0, i/o): serial
0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020102000-000000002010201f (prio 0, i/o): serial
0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020104000-000000002010401f (prio 0, i/o): serial
0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020106000-000000002010601f (prio 0, i/o): serial
0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20210925133407.1259392-3-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
/*
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* Microchip PolarFire SoC MMUART emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "chardev/char.h"
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#include "hw/char/mchp_pfsoc_mmuart.h"
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#define REGS_OFFSET 0x20
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static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
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{
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MchpPfSoCMMUartState *s = opaque;
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addr >>= 2;
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if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return 0;
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}
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return s->reg[addr];
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}
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static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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MchpPfSoCMMUartState *s = opaque;
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uint32_t val32 = (uint32_t)value;
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addr >>= 2;
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if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
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" v=0x%x\n", __func__, addr << 2, val32);
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return;
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}
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s->reg[addr] = val32;
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}
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static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
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.read = mchp_pfsoc_mmuart_read,
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.write = mchp_pfsoc_mmuart_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
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hwaddr base, qemu_irq irq, Chardev *chr)
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{
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MchpPfSoCMMUartState *s;
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s = g_new0(MchpPfSoCMMUartState, 1);
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memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
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memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
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"mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
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memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
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s->base = base;
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s->irq = irq;
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s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
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DEVICE_LITTLE_ENDIAN);
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memory_region_add_subregion(sysmem, base, &s->container);
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return s;
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}
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