qemu/target
Richard Henderson 24c328521b target/openrisc: Tidy ppc/npc implementation
The NPC SPR is really only supposed to be used for FPGA debugging.
It contains the same contents as PC, unless one plays games.  Follow
the or1ksim implementation in flushing delayed branch state when it
is changed.

The PPC SPR need not be updated every instruction, merely when we
exit the TB or attempt to read its contents.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14 08:15:00 +11:00
..
alpha migration: extend VMStateInfo 2017-01-24 17:54:47 +00:00
arm target-arm: Enable vPMU support under TCG mode 2017-02-10 17:40:28 +00:00
cris qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
hppa target/hppa: Fix gdb_write_register 2017-02-06 18:25:31 -08:00
i386 pc: Enable vmware-cpuid-freq CPU option for 2.9+ machine types 2017-01-27 18:07:58 +01:00
lm32 qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
m68k This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
microblaze cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
mips migration: extend VMStateInfo 2017-01-24 17:54:47 +00:00
moxie qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
nios2 nios2: Add architecture emulation support 2017-01-24 13:10:35 -08:00
openrisc target/openrisc: Tidy ppc/npc implementation 2017-02-14 08:15:00 +11:00
ppc ppc/kvm: Handle the "family" CPU via alias instead of registering new types 2017-02-02 09:30:07 +11:00
s390x s390x/kvm: fix cmma reset for KVM 2017-01-24 15:47:31 +01:00
sh4 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
sparc migration: extend VMStateInfo 2017-01-24 17:54:47 +00:00
tilegx qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
tricore qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
unicore32 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
xtensa target/xtensa updates: 2017-01-25 16:36:57 +00:00