qemu/target/riscv
Dayeol Lee 4a9b31b82b
target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR.
The default promotion rules will result in an integer here ("i*8" is integer, which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high bits of the CSR being wrong.

Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-30 11:04:28 -07:00
..
cpu_bits.h RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu_helper.c
cpu_user.h
cpu.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu.h
fpu_helper.c
gdbstub.c
helper.h
instmap.h
Makefile.objs
op_helper.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
pmp.c target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 2018-10-30 11:04:28 -07:00
pmp.h
translate.c