Rob Bradford 2317ba9fa7 target/riscv: Add infrastructure for 'B' MISA extension ... Add the infrastructure for the 'B' extension which is the union of the Zba, Zbb and Zbs instructions. Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240111161644.33630-2-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-02-09 10:39:16 +10:00
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meson.build	target/riscv: introduce TCG AccelCPUClass	2023-10-12 11:55:21 +10:00
tcg-cpu.c	target/riscv: Add infrastructure for 'B' MISA extension	2024-02-09 10:39:16 +10:00
tcg-cpu.h	target/riscv: add riscv_cpu_accelerator_compatible()	2023-11-07 11:06:02 +10:00