0d75590d91
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-6-git-send-email-peter.maydell@linaro.org
525 lines
16 KiB
C
525 lines
16 KiB
C
/*
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* QEMU Uninorth PCI host (for all Mac99 and newer machines)
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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/* debug UniNorth */
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//#define DEBUG_UNIN
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#ifdef DEBUG_UNIN
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#define UNIN_DPRINTF(fmt, ...) \
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do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define UNIN_DPRINTF(fmt, ...)
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#endif
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static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
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#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
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#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
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#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
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#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
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#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
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#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
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OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
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#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
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#define U3_AGP_HOST_BRIDGE(obj) \
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OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
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typedef struct UNINState {
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PCIHostState parent_obj;
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MemoryRegion pci_mmio;
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MemoryRegion pci_hole;
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} UNINState;
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int retval;
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int devfn = pci_dev->devfn & 0x00FFFFFF;
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retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
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return retval;
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}
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static void pci_unin_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
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unin_irq_line[irq_num], level);
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qemu_set_irq(pic[unin_irq_line[irq_num]], level);
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}
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static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
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{
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uint32_t retval;
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if (reg & (1u << 31)) {
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/* XXX OpenBIOS compatibility hack */
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retval = reg | (addr & 3);
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} else if (reg & 1) {
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/* CFA1 style */
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retval = (reg & ~7u) | (addr & 7);
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} else {
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uint32_t slot, func;
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/* Grab CFA0 style values */
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slot = ctz32(reg & 0xfffff800);
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if (slot == 32) {
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slot = -1; /* XXX: should this be 0? */
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}
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func = (reg >> 8) & 7;
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/* ... and then convert them to x86 format */
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/* config pointer */
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retval = (reg & (0xff - 7)) | (addr & 7);
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/* slot */
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retval |= slot << 11;
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/* fn */
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retval |= func << 8;
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}
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UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
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reg, addr, retval);
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return retval;
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}
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static void unin_data_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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UNINState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
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addr, len, val);
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pci_data_write(phb->bus,
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unin_get_config_reg(phb->config_reg, addr),
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val, len);
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}
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static uint64_t unin_data_read(void *opaque, hwaddr addr,
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unsigned len)
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{
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UNINState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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uint32_t val;
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val = pci_data_read(phb->bus,
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unin_get_config_reg(phb->config_reg, addr),
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len);
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UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
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addr, len, val);
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return val;
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}
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static const MemoryRegionOps unin_data_ops = {
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.read = unin_data_read,
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.write = unin_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int pci_unin_main_init_device(SysBusDevice *dev)
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{
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PCIHostState *h;
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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h = PCI_HOST_BRIDGE(dev);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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dev, "pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
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"pci-conf-data", 0x1000);
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sysbus_init_mmio(dev, &h->conf_mem);
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sysbus_init_mmio(dev, &h->data_mem);
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return 0;
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}
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static int pci_u3_agp_init_device(SysBusDevice *dev)
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{
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PCIHostState *h;
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/* Uninorth U3 AGP bus */
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h = PCI_HOST_BRIDGE(dev);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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dev, "pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
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"pci-conf-data", 0x1000);
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sysbus_init_mmio(dev, &h->conf_mem);
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sysbus_init_mmio(dev, &h->data_mem);
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return 0;
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}
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static int pci_unin_agp_init_device(SysBusDevice *dev)
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{
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PCIHostState *h;
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/* Uninorth AGP bus */
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h = PCI_HOST_BRIDGE(dev);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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dev, "pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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dev, "pci-conf-data", 0x1000);
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sysbus_init_mmio(dev, &h->conf_mem);
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sysbus_init_mmio(dev, &h->data_mem);
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return 0;
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}
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static int pci_unin_internal_init_device(SysBusDevice *dev)
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{
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PCIHostState *h;
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/* Uninorth internal bus */
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h = PCI_HOST_BRIDGE(dev);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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dev, "pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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dev, "pci-conf-data", 0x1000);
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sysbus_init_mmio(dev, &h->conf_mem);
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sysbus_init_mmio(dev, &h->data_mem);
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return 0;
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}
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PCIBus *pci_pmac_init(qemu_irq *pic,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io)
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{
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DeviceState *dev;
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SysBusDevice *s;
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PCIHostState *h;
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UNINState *d;
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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h = PCI_HOST_BRIDGE(s);
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d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
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memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
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memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
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0x80000000ULL, 0x10000000ULL);
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memory_region_add_subregion(address_space_mem, 0x80000000ULL,
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&d->pci_hole);
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h->bus = pci_register_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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pic,
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&d->pci_mmio,
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address_space_io,
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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#if 0
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
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#endif
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sysbus_mmio_map(s, 0, 0xf2800000);
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sysbus_mmio_map(s, 1, 0xf2c00000);
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/* DEC 21154 bridge */
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#if 0
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/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
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pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
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#endif
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/* Uninorth AGP bus */
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
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dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(s, 0, 0xf0800000);
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sysbus_mmio_map(s, 1, 0xf0c00000);
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/* Uninorth internal bus */
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#if 0
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/* XXX: not needed for now */
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pci_create_simple(h->bus, PCI_DEVFN(14, 0),
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"uni-north-internal-pci");
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dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(s, 0, 0xf4800000);
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sysbus_mmio_map(s, 1, 0xf4c00000);
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#endif
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return h->bus;
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}
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PCIBus *pci_pmac_u3_init(qemu_irq *pic,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io)
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{
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DeviceState *dev;
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SysBusDevice *s;
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PCIHostState *h;
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UNINState *d;
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/* Uninorth AGP bus */
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dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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h = PCI_HOST_BRIDGE(dev);
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d = U3_AGP_HOST_BRIDGE(dev);
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memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
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memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
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0x80000000ULL, 0x70000000ULL);
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memory_region_add_subregion(address_space_mem, 0x80000000ULL,
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&d->pci_hole);
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h->bus = pci_register_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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pic,
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&d->pci_mmio,
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address_space_io,
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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sysbus_mmio_map(s, 0, 0xf0800000);
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sysbus_mmio_map(s, 1, 0xf0c00000);
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pci_create_simple(h->bus, 11 << 3, "u3-agp");
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return h->bus;
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}
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static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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}
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static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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// d->config[0x34] = 0x80; // capabilities_pointer
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}
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static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache line size */
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d->config[0x0C] = 0x08;
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/* latency timer */
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d->config[0x0D] = 0x10;
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}
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static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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}
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static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_main_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo unin_main_pci_host_info = {
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.name = "uni-north-pci",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_main_pci_host_class_init,
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};
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static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = u3_agp_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo u3_agp_pci_host_info = {
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.name = "u3-agp",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = u3_agp_pci_host_class_init,
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};
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static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_agp_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo unin_agp_pci_host_info = {
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.name = "uni-north-agp",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_agp_pci_host_class_init,
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};
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static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_internal_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo unin_internal_pci_host_info = {
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.name = "uni-north-internal-pci",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_internal_pci_host_class_init,
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};
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static void pci_unin_main_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
sbc->init = pci_unin_main_init_device;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_main_info = {
|
|
.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.class_init = pci_unin_main_class_init,
|
|
};
|
|
|
|
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
sbc->init = pci_u3_agp_init_device;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_u3_agp_info = {
|
|
.name = TYPE_U3_AGP_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.class_init = pci_u3_agp_class_init,
|
|
};
|
|
|
|
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
sbc->init = pci_unin_agp_init_device;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_agp_info = {
|
|
.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.class_init = pci_unin_agp_class_init,
|
|
};
|
|
|
|
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
sbc->init = pci_unin_internal_init_device;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_internal_info = {
|
|
.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINState),
|
|
.class_init = pci_unin_internal_class_init,
|
|
};
|
|
|
|
static void unin_register_types(void)
|
|
{
|
|
type_register_static(&unin_main_pci_host_info);
|
|
type_register_static(&u3_agp_pci_host_info);
|
|
type_register_static(&unin_agp_pci_host_info);
|
|
type_register_static(&unin_internal_pci_host_info);
|
|
|
|
type_register_static(&pci_unin_main_info);
|
|
type_register_static(&pci_u3_agp_info);
|
|
type_register_static(&pci_unin_agp_info);
|
|
type_register_static(&pci_unin_internal_info);
|
|
}
|
|
|
|
type_init(unin_register_types)
|