Peter Maydell 056f43df91 armv7m: R14 should reset to 0xffffffff ... For M profile (unlike A profile) the reset value of R14 is specified as 0xffffffff. (The rationale is that this is an illegal exception return value, so if guest code tries to return to it it will result in a helpful exception.) Registers r0 to r12 and the flags are architecturally UNKNOWN on reset, so we leave those at zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-11-git-send-email-peter.maydell@linaro.org		2017-01-27 15:29:08 +00:00
..
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
arm-semi.c
cpu64.c	target-arm: Enable EL2 feature bit on A53 and A57	2017-01-20 11:15:10 +00:00
cpu-qom.h
cpu.c	armv7m: R14 should reset to 0xffffffff	2017-01-27 15:29:08 +00:00
cpu.h	armv7m: Report no-coprocessor faults correctly	2017-01-27 15:29:08 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper.c	armv7m: Report no-coprocessor faults correctly	2017-01-27 15:29:08 +00:00
helper.h
internals.h	armv7m: Fix reads of CONTROL register bit 1	2017-01-27 15:20:21 +00:00
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c	armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR	2017-01-27 15:29:08 +00:00
Makefile.objs
monitor.c
neon_helper.c
op_addsub.h
op_helper.c
psci.c	target/arm/psci.c: If EL2 implemented, start CPUs in EL2	2017-01-20 11:15:10 +00:00
trace-events
translate-a64.c
translate.c	armv7m: Report no-coprocessor faults correctly	2017-01-27 15:29:08 +00:00
translate.h