c752bb079b
This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-9-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*
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* Nuvoton NPCM7xx OTP (Fuse Array) Interface
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_OTP_H
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#define NPCM7XX_OTP_H
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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/* Each OTP module holds 8192 bits of one-time programmable storage */
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#define NPCM7XX_OTP_ARRAY_BITS (8192)
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#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / BITS_PER_BYTE)
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/* Fuse array offsets */
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#define NPCM7XX_FUSE_FUSTRAP (0)
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#define NPCM7XX_FUSE_CP_FUSTRAP (12)
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#define NPCM7XX_FUSE_DAC_CALIB (16)
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#define NPCM7XX_FUSE_ADC_CALIB (24)
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#define NPCM7XX_FUSE_DERIVATIVE (64)
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#define NPCM7XX_FUSE_TEST_SIG (72)
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#define NPCM7XX_FUSE_DIE_LOCATION (74)
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#define NPCM7XX_FUSE_GP1 (80)
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#define NPCM7XX_FUSE_GP2 (128)
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_OTP_NR_REGS (0x18 / sizeof(uint32_t))
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/**
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* struct NPCM7xxOTPState - Device state for one OTP module.
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* @parent: System bus device.
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* @mmio: Memory region through which registers are accessed.
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* @regs: Register contents.
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* @array: OTP storage array.
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*/
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typedef struct NPCM7xxOTPState {
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SysBusDevice parent;
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MemoryRegion mmio;
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uint32_t regs[NPCM7XX_OTP_NR_REGS];
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uint8_t array[NPCM7XX_OTP_ARRAY_BYTES];
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} NPCM7xxOTPState;
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#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
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#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
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#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
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#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
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typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
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/**
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* npcm7xx_otp_array_write - ECC encode and write data to OTP array.
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* @s: OTP module.
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* @data: Data to be encoded and written.
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* @offset: Offset of first byte to be written in the OTP array.
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* @len: Number of bytes before ECC encoding.
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*
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* Each nibble of data is encoded into a byte, so the number of bytes written
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* to the array will be @len * 2.
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*/
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extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
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unsigned int offset, unsigned int len);
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#endif /* NPCM7XX_OTP_H */
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