689 lines
23 KiB
C
689 lines
23 KiB
C
/*
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* QEMU PowerPC e500-based platforms
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "e500.h"
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#include "e500-ccsr.h"
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#include "net/net.h"
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#include "qemu/config-file.h"
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#include "hw/hw.h"
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#include "hw/serial.h"
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#include "hw/pci/pci.h"
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#include "hw/boards.h"
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#include "sysemu.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
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#include "device_tree.h"
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#include "hw/openpic.h"
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#include "hw/ppc.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "qemu/host-utils.h"
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#include "hw/ppce500_pci.h"
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#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
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#define UIMAGE_LOAD_BASE 0
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#define DTC_LOAD_PAD 0x1800000
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#define DTC_PAD_MASK 0xFFFFF
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#define INITRD_LOAD_PAD 0x2000000
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#define INITRD_PAD_MASK 0xFFFFFF
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#define RAM_SIZES_ALIGN (64UL << 20)
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/* TODO: parameterize */
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#define MPC8544_CCSRBAR_BASE 0xE0000000ULL
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#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
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#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
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#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
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#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
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#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
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#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
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MPC8544_PCI_REGS_OFFSET)
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#define MPC8544_PCI_REGS_SIZE 0x1000ULL
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#define MPC8544_PCI_IO 0xE1000000ULL
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#define MPC8544_UTIL_OFFSET 0xe0000ULL
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#define MPC8544_SPIN_BASE 0xEF000000ULL
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struct boot_info
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{
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uint32_t dt_base;
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uint32_t dt_size;
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uint32_t entry;
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};
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static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
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int nr_slots, int *len)
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{
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int i = 0;
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int slot;
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int pci_irq;
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int host_irq;
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int last_slot = first_slot + nr_slots;
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uint32_t *pci_map;
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*len = nr_slots * 4 * 7 * sizeof(uint32_t);
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pci_map = g_malloc(*len);
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for (slot = first_slot; slot < last_slot; slot++) {
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for (pci_irq = 0; pci_irq < 4; pci_irq++) {
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pci_map[i++] = cpu_to_be32(slot << 11);
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pci_map[i++] = cpu_to_be32(0x0);
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pci_map[i++] = cpu_to_be32(0x0);
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pci_map[i++] = cpu_to_be32(pci_irq + 1);
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pci_map[i++] = cpu_to_be32(mpic);
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host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
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pci_map[i++] = cpu_to_be32(host_irq + 1);
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pci_map[i++] = cpu_to_be32(0x1);
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}
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}
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assert((i * sizeof(uint32_t)) == *len);
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return pci_map;
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}
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static void dt_serial_create(void *fdt, unsigned long long offset,
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const char *soc, const char *mpic,
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const char *alias, int idx, bool defcon)
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{
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char ser[128];
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snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
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qemu_devtree_add_subnode(fdt, ser);
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qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
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qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
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qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
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qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
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qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
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qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2);
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qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
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qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
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if (defcon) {
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qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
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}
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}
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static int ppce500_load_device_tree(CPUPPCState *env,
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PPCE500Params *params,
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hwaddr addr,
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hwaddr initrd_base,
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hwaddr initrd_size)
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{
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int ret = -1;
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uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
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int fdt_size;
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void *fdt;
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uint8_t hypercall[16];
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uint32_t clock_freq = 400000000;
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uint32_t tb_freq = 400000000;
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int i;
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const char *toplevel_compat = NULL; /* user override */
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char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
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char soc[128];
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char mpic[128];
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uint32_t mpic_ph;
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uint32_t msi_ph;
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char gutil[128];
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char pci[128];
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char msi[128];
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uint32_t *pci_map = NULL;
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int len;
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uint32_t pci_ranges[14] =
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{
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0x2000000, 0x0, 0xc0000000,
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0x0, 0xc0000000,
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0x0, 0x20000000,
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0x1000000, 0x0, 0x0,
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0x0, 0xe1000000,
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0x0, 0x10000,
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};
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QemuOpts *machine_opts;
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const char *dtb_file = NULL;
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machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
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if (machine_opts) {
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dtb_file = qemu_opt_get(machine_opts, "dtb");
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toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
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}
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if (dtb_file) {
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char *filename;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
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if (!filename) {
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goto out;
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}
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fdt = load_device_tree(filename, &fdt_size);
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if (!fdt) {
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goto out;
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}
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goto done;
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}
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fdt = create_device_tree(&fdt_size);
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if (fdt == NULL) {
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goto out;
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}
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/* Manipulate device tree in memory. */
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qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
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qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
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qemu_devtree_add_subnode(fdt, "/memory");
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qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
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qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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qemu_devtree_add_subnode(fdt, "/chosen");
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if (initrd_size) {
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (ret < 0) {
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fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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}
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (ret < 0) {
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fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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}
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}
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ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
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params->kernel_cmdline);
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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if (kvm_enabled()) {
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/* Read out host's frequencies */
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clock_freq = kvmppc_get_clockfreq();
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tb_freq = kvmppc_get_tbfreq();
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/* indicate KVM hypercall interface */
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qemu_devtree_add_subnode(fdt, "/hypervisor");
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qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
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"linux,kvm");
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kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
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qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
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hypercall, sizeof(hypercall));
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}
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/* Create CPU nodes */
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qemu_devtree_add_subnode(fdt, "/cpus");
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qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
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qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
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/* We need to generate the cpu nodes in reverse order, so Linux can pick
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the first node as boot node and be happy */
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for (i = smp_cpus - 1; i >= 0; i--) {
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char cpu_name[128];
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uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
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for (env = first_cpu; env != NULL; env = env->next_cpu) {
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if (env->cpu_index == i) {
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break;
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}
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}
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if (!env) {
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continue;
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}
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snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
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qemu_devtree_add_subnode(fdt, cpu_name);
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qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
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qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
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qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
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qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
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qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
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env->dcache_line_size);
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qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
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env->icache_line_size);
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qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
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qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
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qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
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if (env->cpu_index) {
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qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
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qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
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qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
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cpu_release_addr);
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} else {
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qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
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}
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}
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qemu_devtree_add_subnode(fdt, "/aliases");
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/* XXX These should go into their respective devices' code */
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snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
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qemu_devtree_add_subnode(fdt, soc);
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qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
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qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
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sizeof(compatible_sb));
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qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
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qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
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qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
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MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
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MPC8544_CCSRBAR_SIZE);
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/* XXX should contain a reasonable value */
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qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
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snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
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qemu_devtree_add_subnode(fdt, mpic);
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qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
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qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
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qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
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0x40000);
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qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
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qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
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mpic_ph = qemu_devtree_alloc_phandle(fdt);
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qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
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qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
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qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
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/*
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* We have to generate ser1 first, because Linux takes the first
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* device it finds in the dt as serial output device. And we generate
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* devices in reverse order to the dt.
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*/
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dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
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soc, mpic, "serial1", 1, false);
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dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
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soc, mpic, "serial0", 0, true);
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snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
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MPC8544_UTIL_OFFSET);
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qemu_devtree_add_subnode(fdt, gutil);
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qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
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qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
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qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
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snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
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qemu_devtree_add_subnode(fdt, msi);
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qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
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qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
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msi_ph = qemu_devtree_alloc_phandle(fdt);
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qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
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qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
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qemu_devtree_setprop_cells(fdt, msi, "interrupts",
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0xe0, 0x0,
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0xe1, 0x0,
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0xe2, 0x0,
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0xe3, 0x0,
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0xe4, 0x0,
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0xe5, 0x0,
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0xe6, 0x0,
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0xe7, 0x0);
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qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
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qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
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snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
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qemu_devtree_add_subnode(fdt, pci);
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qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
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qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
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qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
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qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
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0x0, 0x7);
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pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
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params->pci_first_slot, params->pci_nr_slots,
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&len);
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qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
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qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
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qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
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qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
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for (i = 0; i < 14; i++) {
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pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
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}
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qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
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qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
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qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
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MPC8544_PCI_REGS_BASE, 0, 0x1000);
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qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
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qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
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qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
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qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
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qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
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params->fixup_devtree(params, fdt);
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if (toplevel_compat) {
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qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat,
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strlen(toplevel_compat) + 1);
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}
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done:
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qemu_devtree_dumpdtb(fdt, fdt_size);
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ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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if (ret < 0) {
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goto out;
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}
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g_free(fdt);
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ret = fdt_size;
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out:
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g_free(pci_map);
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return ret;
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}
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/* Create -kernel TLB entries for BookE. */
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static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
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{
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return 63 - clz64(size >> 10);
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}
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static void mmubooke_create_initial_mapping(CPUPPCState *env)
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{
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struct boot_info *bi = env->load_info;
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ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
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hwaddr size, dt_end;
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int ps;
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/* Our initial TLB entry needs to cover everything from 0 to
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the device tree top */
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dt_end = bi->dt_base + bi->dt_size;
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ps = booke206_page_size_to_tlb(dt_end) + 1;
|
|
if (ps & 1) {
|
|
/* e500v2 can only do even TLB size bits */
|
|
ps++;
|
|
}
|
|
size = (ps << MAS1_TSIZE_SHIFT);
|
|
tlb->mas1 = MAS1_VALID | size;
|
|
tlb->mas2 = 0;
|
|
tlb->mas7_3 = 0;
|
|
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
|
|
|
|
env->tlb_dirty = true;
|
|
}
|
|
|
|
static void ppce500_cpu_reset_sec(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
/* Secondary CPU starts in halted state for now. Needs to change when
|
|
implementing non-kernel boot. */
|
|
env->halted = 1;
|
|
env->exception_index = EXCP_HLT;
|
|
}
|
|
|
|
static void ppce500_cpu_reset(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
CPUPPCState *env = &cpu->env;
|
|
struct boot_info *bi = env->load_info;
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
/* Set initial guest state. */
|
|
env->halted = 0;
|
|
env->gpr[1] = (16<<20) - 8;
|
|
env->gpr[3] = bi->dt_base;
|
|
env->nip = bi->entry;
|
|
mmubooke_create_initial_mapping(env);
|
|
}
|
|
|
|
void ppce500_init(PPCE500Params *params)
|
|
{
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
PCIBus *pci_bus;
|
|
CPUPPCState *env = NULL;
|
|
uint64_t elf_entry;
|
|
uint64_t elf_lowaddr;
|
|
hwaddr entry=0;
|
|
hwaddr loadaddr=UIMAGE_LOAD_BASE;
|
|
target_long kernel_size=0;
|
|
target_ulong dt_base = 0;
|
|
target_ulong initrd_base = 0;
|
|
target_long initrd_size=0;
|
|
int i = 0, j, k;
|
|
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
|
|
qemu_irq **irqs, *mpic;
|
|
DeviceState *dev;
|
|
CPUPPCState *firstenv = NULL;
|
|
MemoryRegion *ccsr_addr_space;
|
|
SysBusDevice *s;
|
|
PPCE500CCSRState *ccsr;
|
|
|
|
/* Setup CPUs */
|
|
if (params->cpu_model == NULL) {
|
|
params->cpu_model = "e500v2_v30";
|
|
}
|
|
|
|
irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
|
|
irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
PowerPCCPU *cpu;
|
|
qemu_irq *input;
|
|
|
|
cpu = cpu_ppc_init(params->cpu_model);
|
|
if (cpu == NULL) {
|
|
fprintf(stderr, "Unable to initialize CPU!\n");
|
|
exit(1);
|
|
}
|
|
env = &cpu->env;
|
|
|
|
if (!firstenv) {
|
|
firstenv = env;
|
|
}
|
|
|
|
irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
|
input = (qemu_irq *)env->irq_inputs;
|
|
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
|
|
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
|
|
env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
|
|
env->mpic_cpu_base = MPC8544_CCSRBAR_BASE +
|
|
MPC8544_MPIC_REGS_OFFSET + 0x20000;
|
|
|
|
ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
|
|
|
|
/* Register reset handler */
|
|
if (!i) {
|
|
/* Primary CPU */
|
|
struct boot_info *boot_info;
|
|
boot_info = g_malloc0(sizeof(struct boot_info));
|
|
qemu_register_reset(ppce500_cpu_reset, cpu);
|
|
env->load_info = boot_info;
|
|
} else {
|
|
/* Secondary CPUs */
|
|
qemu_register_reset(ppce500_cpu_reset_sec, cpu);
|
|
}
|
|
}
|
|
|
|
env = firstenv;
|
|
|
|
/* Fixup Memory size on a alignment boundary */
|
|
ram_size &= ~(RAM_SIZES_ALIGN - 1);
|
|
|
|
/* Register Memory */
|
|
memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
|
|
vmstate_register_ram_global(ram);
|
|
memory_region_add_subregion(address_space_mem, 0, ram);
|
|
|
|
dev = qdev_create(NULL, "e500-ccsr");
|
|
object_property_add_child(qdev_get_machine(), "e500-ccsr",
|
|
OBJECT(dev), NULL);
|
|
qdev_init_nofail(dev);
|
|
ccsr = CCSR(dev);
|
|
ccsr_addr_space = &ccsr->ccsr_space;
|
|
memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
|
|
ccsr_addr_space);
|
|
|
|
/* MPIC */
|
|
mpic = g_new(qemu_irq, 256);
|
|
dev = qdev_create(NULL, "openpic");
|
|
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
|
|
qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
|
|
qdev_init_nofail(dev);
|
|
s = sysbus_from_qdev(dev);
|
|
|
|
k = 0;
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
|
|
sysbus_connect_irq(s, k++, irqs[i][j]);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 256; i++) {
|
|
mpic[i] = qdev_get_gpio_in(dev, i);
|
|
}
|
|
|
|
memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
|
|
s->mmio[0].memory);
|
|
|
|
/* Serial */
|
|
if (serial_hds[0]) {
|
|
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
|
|
0, mpic[42], 399193,
|
|
serial_hds[0], DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
if (serial_hds[1]) {
|
|
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
|
|
0, mpic[42], 399193,
|
|
serial_hds[1], DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
/* General Utility device */
|
|
dev = qdev_create(NULL, "mpc8544-guts");
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
/* PCI */
|
|
dev = qdev_create(NULL, "e500-pcihost");
|
|
qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
|
|
sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
|
|
sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
|
|
sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
|
|
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
|
if (!pci_bus)
|
|
printf("couldn't create PCI controller!\n");
|
|
|
|
sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO);
|
|
|
|
if (pci_bus) {
|
|
/* Register network interfaces. */
|
|
for (i = 0; i < nb_nics; i++) {
|
|
pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
|
|
}
|
|
}
|
|
|
|
/* Register spinning region */
|
|
sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
|
|
|
|
/* Load kernel. */
|
|
if (params->kernel_filename) {
|
|
kernel_size = load_uimage(params->kernel_filename, &entry,
|
|
&loadaddr, NULL);
|
|
if (kernel_size < 0) {
|
|
kernel_size = load_elf(params->kernel_filename, NULL, NULL,
|
|
&elf_entry, &elf_lowaddr, NULL, 1,
|
|
ELF_MACHINE, 0);
|
|
entry = elf_entry;
|
|
loadaddr = elf_lowaddr;
|
|
}
|
|
/* XXX try again as binary */
|
|
if (kernel_size < 0) {
|
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
params->kernel_filename);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Load initrd. */
|
|
if (params->initrd_filename) {
|
|
initrd_base = (loadaddr + kernel_size + INITRD_LOAD_PAD) &
|
|
~INITRD_PAD_MASK;
|
|
initrd_size = load_image_targphys(params->initrd_filename, initrd_base,
|
|
ram_size - initrd_base);
|
|
|
|
if (initrd_size < 0) {
|
|
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
|
params->initrd_filename);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* If we're loading a kernel directly, we must load the device tree too. */
|
|
if (params->kernel_filename) {
|
|
struct boot_info *boot_info;
|
|
int dt_size;
|
|
|
|
dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
|
|
dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base,
|
|
initrd_size);
|
|
if (dt_size < 0) {
|
|
fprintf(stderr, "couldn't load device tree\n");
|
|
exit(1);
|
|
}
|
|
|
|
boot_info = env->load_info;
|
|
boot_info->entry = entry;
|
|
boot_info->dt_base = dt_base;
|
|
boot_info->dt_size = dt_size;
|
|
}
|
|
|
|
if (kvm_enabled()) {
|
|
kvmppc_init();
|
|
}
|
|
}
|
|
|
|
static int e500_ccsr_initfn(SysBusDevice *dev)
|
|
{
|
|
PPCE500CCSRState *ccsr;
|
|
|
|
ccsr = CCSR(dev);
|
|
memory_region_init(&ccsr->ccsr_space, "e500-ccsr",
|
|
MPC8544_CCSRBAR_SIZE);
|
|
return 0;
|
|
}
|
|
|
|
static void e500_ccsr_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
k->init = e500_ccsr_initfn;
|
|
}
|
|
|
|
static const TypeInfo e500_ccsr_info = {
|
|
.name = TYPE_CCSR,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PPCE500CCSRState),
|
|
.class_init = e500_ccsr_class_init,
|
|
};
|
|
|
|
static void e500_register_types(void)
|
|
{
|
|
type_register_static(&e500_ccsr_info);
|
|
}
|
|
|
|
type_init(e500_register_types)
|