c0c0461e3a
The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn> Message-Id: <20230822071959.35620-3-philmd@linaro.org>
190 lines
5.4 KiB
C++
190 lines
5.4 KiB
C++
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
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addr = make_address_i(ctx, addr, a->imm);
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tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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{
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TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
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addr = make_address_i(ctx, addr, a->imm);
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tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
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return true;
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}
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static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
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TCGv addr = make_address_x(ctx, src1, src2);
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tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)
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{
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TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
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TCGv addr = make_address_x(ctx, src1, src2);
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tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
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return true;
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}
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static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
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gen_helper_asrtgt_d(cpu_env, src1, src2);
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src1 = make_address_i(ctx, src1, 0);
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tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
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gen_helper_asrtle_d(cpu_env, src1, src2);
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src1 = make_address_i(ctx, src1, 0);
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tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
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{
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TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
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gen_helper_asrtgt_d(cpu_env, src1, src2);
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src1 = make_address_i(ctx, src1, 0);
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tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
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return true;
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}
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static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
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{
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TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
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gen_helper_asrtle_d(cpu_env, src1, src2);
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src1 = make_address_i(ctx, src1, 0);
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tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
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return true;
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}
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static bool trans_preld(DisasContext *ctx, arg_preld *a)
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{
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return true;
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}
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static bool trans_dbar(DisasContext *ctx, arg_dbar * a)
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{
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tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
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return true;
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}
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static bool trans_ibar(DisasContext *ctx, arg_ibar *a)
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{
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ctx->base.is_jmp = DISAS_STOP;
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return true;
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}
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static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
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addr = make_address_i(ctx, addr, a->imm);
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tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
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{
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TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
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addr = make_address_i(ctx, addr, a->imm);
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tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
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return true;
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}
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TRANS(ld_b, ALL, gen_load, MO_SB)
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TRANS(ld_h, ALL, gen_load, MO_TESW)
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TRANS(ld_w, ALL, gen_load, MO_TESL)
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TRANS(ld_d, 64, gen_load, MO_TEUQ)
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TRANS(st_b, ALL, gen_store, MO_UB)
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TRANS(st_h, ALL, gen_store, MO_TEUW)
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TRANS(st_w, ALL, gen_store, MO_TEUL)
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TRANS(st_d, 64, gen_store, MO_TEUQ)
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TRANS(ld_bu, ALL, gen_load, MO_UB)
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TRANS(ld_hu, ALL, gen_load, MO_TEUW)
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TRANS(ld_wu, 64, gen_load, MO_TEUL)
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TRANS(ldx_b, 64, gen_loadx, MO_SB)
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TRANS(ldx_h, 64, gen_loadx, MO_TESW)
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TRANS(ldx_w, 64, gen_loadx, MO_TESL)
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TRANS(ldx_d, 64, gen_loadx, MO_TEUQ)
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TRANS(stx_b, 64, gen_storex, MO_UB)
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TRANS(stx_h, 64, gen_storex, MO_TEUW)
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TRANS(stx_w, 64, gen_storex, MO_TEUL)
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TRANS(stx_d, 64, gen_storex, MO_TEUQ)
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TRANS(ldx_bu, 64, gen_loadx, MO_UB)
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TRANS(ldx_hu, 64, gen_loadx, MO_TEUW)
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TRANS(ldx_wu, 64, gen_loadx, MO_TEUL)
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TRANS(ldptr_w, 64, gen_ldptr, MO_TESL)
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TRANS(stptr_w, 64, gen_stptr, MO_TEUL)
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TRANS(ldptr_d, 64, gen_ldptr, MO_TEUQ)
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TRANS(stptr_d, 64, gen_stptr, MO_TEUQ)
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TRANS(ldgt_b, 64, gen_load_gt, MO_SB)
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TRANS(ldgt_h, 64, gen_load_gt, MO_TESW)
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TRANS(ldgt_w, 64, gen_load_gt, MO_TESL)
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TRANS(ldgt_d, 64, gen_load_gt, MO_TEUQ)
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TRANS(ldle_b, 64, gen_load_le, MO_SB)
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TRANS(ldle_h, 64, gen_load_le, MO_TESW)
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TRANS(ldle_w, 64, gen_load_le, MO_TESL)
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TRANS(ldle_d, 64, gen_load_le, MO_TEUQ)
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TRANS(stgt_b, 64, gen_store_gt, MO_UB)
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TRANS(stgt_h, 64, gen_store_gt, MO_TEUW)
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TRANS(stgt_w, 64, gen_store_gt, MO_TEUL)
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TRANS(stgt_d, 64, gen_store_gt, MO_TEUQ)
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TRANS(stle_b, 64, gen_store_le, MO_UB)
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TRANS(stle_h, 64, gen_store_le, MO_TEUW)
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TRANS(stle_w, 64, gen_store_le, MO_TEUL)
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TRANS(stle_d, 64, gen_store_le, MO_TEUQ)
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