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1c6b2e4b79
qemu/target/tricore
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Bastian Koppelmann 1c6b2e4b79 target/tricore: Fix OPC2_32_RCRW_INSERT translation 
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08 09:57:42 +01:00
..
cpu-param.h Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
cpu-qom.h target/tricore: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
cpu.c target/tricore: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
cpu.h Move CPU softfloat unions to cpu-float.h 2022-04-06 14:31:43 +02:00
csfr.h.inc target/tricore: Rename csfr.def -> csfr.h.inc 2022-11-05 20:35:45 +01:00
fpu_helper.c tricore: add QSEED instruction 2019-06-25 15:02:07 +02:00
gdbstub.c target/tricore: Fix gdbstub write to address registers 2022-12-18 09:39:17 -08:00
helper.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
helper.h target/tricore: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
op_helper.c accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
translate.c target/tricore: Fix OPC2_32_RCRW_INSERT translation 2023-02-08 09:57:42 +01:00
tricore-defs.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
tricore-opcodes.h Supply missing header guards 2019-06-12 13:20:21 +02:00