mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
qemu/target
History
Alistair Francis 1c1c060aa8 target/riscv: Remove the HS_TWO_STAGE flag 
The HS_TWO_STAGE flag is no longer required as the MMU index contains
the information if we are performing a two stage access.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f514b128b1ff0fb41c85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
2020-11-09 15:08:53 -08:00
..
alpha
cpu-timers, icount: new modules
2020-10-05 16:41:22 +02:00
arm
target/arm: Get correct MMU index for other-security-state
2020-11-02 16:52:17 +00:00
avr
…
cris
…
hppa
qemu/atomic.h: rename atomic_ to qatomic_
2020-09-23 16:07:44 +01:00
i386
* Drop ninjatool and just require ninja (Paolo)
2020-10-17 20:52:55 +01:00
lm32
…
m68k
…
microblaze
…
mips
target/mips: Add unaligned access support for MIPS64R6 and Loongson-3
2020-11-03 16:51:13 +01:00
moxie
…
nios2
…
openrisc
…
ppc
ppc/: fix some comment spelling errors
2020-10-28 01:08:53 +11:00
riscv
target/riscv: Remove the HS_TWO_STAGE flag
2020-11-09 15:08:53 -08:00
rx
target/rx: Fix Lesser GPL version number
2020-10-27 00:22:56 +01:00
s390x
s390x: pv: Fix diag318 PV fencing
2020-10-22 15:47:27 +02:00
sh4
target/sh4: fix some comment spelling errors
2020-10-27 00:22:56 +01:00
sparc
target/sparc/int32_helper: Remove duplicated 'Tag Overflow' entry
2020-10-13 13:33:46 +02:00
tilegx
…
tricore
…
unicore32
…
xtensa
target/xtensa: enable all coprocessors for linux-user
2020-10-26 12:07:19 +01:00
meson.build
…