Peter Maydell 1b15a97d4c target/arm: Implement MVE shift-by-scalar ... Implement the MVE instructions which perform shifts by a scalar. These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2. They take the shift amount in a general purpose register and shift every element in the vector by that amount. Mostly we can reuse the helper functions for shift-by-immediate; we do need two new helpers for VQRSHL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>		2021-08-25 10:48:49 +01:00
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Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
a32-uncond.decode	…
a32.decode	…
arch_dump.c	…
arm-powerctl.c	…
arm-powerctl.h	…
arm_ldst.h	…
cpu-param.h	…
cpu-qom.h	…
cpu.c	target/arm: Print MVE VPR in CPU dumps	2021-08-25 10:48:48 +01:00
cpu.h	target/arm: Add sve-default-vector-length cpu property	2021-07-27 10:57:40 +01:00
cpu64.c	target/arm: Add sve-default-vector-length cpu property	2021-07-27 10:57:40 +01:00
cpu_tcg.c	target/arm: Implement debug_check_breakpoint	2021-07-21 07:47:04 -10:00
crypto_helper.c	…
debug_helper.c	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00
gdbstub.c	target/arm: Enforce that M-profile SP low 2 bits are always zero	2021-07-27 10:57:39 +01:00
gdbstub64.c	…
helper-a64.c	tcg: Rename helper_atomic_*_mmu and provide for user-only	2021-07-21 07:45:38 -10:00
helper-a64.h	…
helper-mve.h	target/arm: Implement MVE shift-by-scalar	2021-08-25 10:48:49 +01:00
helper-sve.h	…
helper.c	target/arm: Export aarch64_sve_zcr_get_valid_len	2021-07-27 10:57:40 +01:00
helper.h	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00
idau.h	…
internals.h	target/arm: Export aarch64_sve_zcr_get_valid_len	2021-07-27 10:57:40 +01:00
iwmmxt_helper.c	…
kvm-consts.h	…
kvm-stub.c	…
kvm.c	…
kvm64.c	…
kvm_arm.h	…
m-nocp.decode	…
m_helper.c	target/arm: Report M-profile alignment faults correctly to the guest	2021-07-27 10:57:39 +01:00
machine.c	…
meson.build	…
monitor.c	…
mte_helper.c	target/arm: Implement MTE3	2021-06-24 14:58:48 +01:00
mve.decode	target/arm: Implement MVE shift-by-scalar	2021-08-25 10:48:49 +01:00
mve_helper.c	target/arm: Implement MVE shift-by-scalar	2021-08-25 10:48:49 +01:00
neon-dp.decode	…
neon-ls.decode	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
neon-shared.decode	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
neon_helper.c	…
op_addsub.h	…
op_helper.c	…
pauth_helper.c	…
psci.c	…
sve.decode	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
sve_helper.c	…
syndrome.h	…
t16.decode	…
t32.decode	target/arm: Implement MVE shifts by register	2021-07-02 11:48:38 +01:00
tlb_helper.c	…
trace-events	…
trace.h	…
translate-a32.h	target/arm: Make VMOV scalar <-> gpreg beatwise for MVE	2021-06-24 14:58:48 +01:00
translate-a64.c	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00
translate-a64.h	…
translate-m-nocp.c	…
translate-mve.c	target/arm: Implement MVE shift-by-scalar	2021-08-25 10:48:49 +01:00
translate-neon.c	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
translate-sve.c	target/arm: Remove duplicate 'plus1' function from Neon and SVE decode	2021-07-18 10:59:47 +01:00
translate-vfp.c	target/arm: Make VMOV scalar <-> gpreg beatwise for MVE	2021-06-24 14:58:48 +01:00
translate.c	target/arm: Enforce that M-profile SP low 2 bits are always zero	2021-07-27 10:57:39 +01:00
translate.h	target/arm: Implement MVE shifts by register	2021-07-02 11:48:38 +01:00
vec_helper.c	target/arm: Implement MVE VMULL (polynomial)	2021-08-25 10:48:49 +01:00
vec_internal.h	target/arm: Implement MVE VMULL (polynomial)	2021-08-25 10:48:49 +01:00
vfp-uncond.decode	…
vfp.decode	…
vfp_helper.c	target/arm: Check NaN mode before silencing NaN	2021-07-02 11:48:36 +01:00