48531f5adb
'svade' is a RVA22S64 profile requirement, a profile we're going to add shortly. It is a named feature (i.e. not a formal extension, not defined in riscv,isa DT at this moment) defined in [1] as: "Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.". As far as the spec goes, 'svade' is one of the two distinct modes of handling PTE_A and PTE_D. The other way, i.e. update PTE_A/PTE_D when they're cleared, is defined by the 'svadu' extension. Checking cpu_helper.c, get_physical_address(), we can verify that QEMU is compliant with that: we will update PTE_A/PTE_D if 'svadu' is enabled, or throw a page-fault exception if 'svadu' isn't enabled. So, as far as we're concerned, 'svade' translates to 'svadu must be disabled'. We'll implement it like 'zic64b': an internal flag that profiles can enable. The flag will not be exposed to users. [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218125334.37184-20-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
202 lines
4.9 KiB
C
202 lines
4.9 KiB
C
/*
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* QEMU RISC-V CPU CFG
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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* Copyright (c) 2021-2023 PLCT Lab
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_CFG_H
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#define RISCV_CPU_CFG_H
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/*
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* map is a 16-bit bitmap: the most significant set bit in map is the maximum
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* satp mode that is supported. It may be chosen by the user and must respect
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* what qemu implements (valid_1_10_32/64) and what the hw is capable of
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* (supported bitmap below).
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*
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* init is a 16-bit bitmap used to make sure the user selected a correct
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* configuration as per the specification.
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*
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* supported is a 16-bit bitmap used to reflect the hw capabilities.
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*/
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typedef struct {
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uint16_t map, init, supported;
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} RISCVSATPMap;
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struct RISCVCPUConfig {
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bool ext_zba;
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bool ext_zbb;
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bool ext_zbc;
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bool ext_zbkb;
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bool ext_zbkc;
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bool ext_zbkx;
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bool ext_zbs;
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bool ext_zca;
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bool ext_zcb;
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bool ext_zcd;
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bool ext_zce;
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bool ext_zcf;
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bool ext_zcmp;
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bool ext_zcmt;
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bool ext_zk;
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bool ext_zkn;
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bool ext_zknd;
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bool ext_zkne;
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bool ext_zknh;
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bool ext_zkr;
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bool ext_zks;
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bool ext_zksed;
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bool ext_zksh;
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bool ext_zkt;
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bool ext_zifencei;
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bool ext_zicntr;
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bool ext_zicsr;
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bool ext_zicbom;
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bool ext_zicbop;
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bool ext_zicboz;
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bool ext_zicond;
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bool ext_zihintntl;
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bool ext_zihintpause;
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bool ext_zihpm;
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bool ext_smstateen;
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bool ext_sstc;
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bool ext_svadu;
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bool ext_svinval;
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bool ext_svnapot;
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bool ext_svpbmt;
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bool ext_zdinx;
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bool ext_zacas;
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bool ext_zawrs;
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bool ext_zfa;
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bool ext_zfbfmin;
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bool ext_zfh;
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bool ext_zfhmin;
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bool ext_zfinx;
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bool ext_zhinx;
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bool ext_zhinxmin;
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bool ext_zve32f;
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bool ext_zve64f;
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bool ext_zve64d;
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bool ext_zvbb;
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bool ext_zvbc;
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bool ext_zvkb;
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bool ext_zvkg;
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bool ext_zvkned;
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bool ext_zvknha;
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bool ext_zvknhb;
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bool ext_zvksed;
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bool ext_zvksh;
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bool ext_zvkt;
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bool ext_zvkn;
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bool ext_zvknc;
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bool ext_zvkng;
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bool ext_zvks;
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bool ext_zvksc;
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bool ext_zvksg;
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bool ext_zmmul;
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bool ext_zvfbfmin;
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bool ext_zvfbfwma;
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bool ext_zvfh;
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bool ext_zvfhmin;
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bool ext_smaia;
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bool ext_ssaia;
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bool ext_sscofpmf;
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bool ext_smepmp;
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bool rvv_ta_all_1s;
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bool rvv_ma_all_1s;
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bool svade;
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bool zic64b;
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uint32_t mvendorid;
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uint64_t marchid;
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uint64_t mimpid;
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/* Vendor-specific custom extensions */
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bool ext_xtheadba;
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bool ext_xtheadbb;
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bool ext_xtheadbs;
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bool ext_xtheadcmo;
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bool ext_xtheadcondmov;
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bool ext_xtheadfmemidx;
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bool ext_xtheadfmv;
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bool ext_xtheadmac;
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bool ext_xtheadmemidx;
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bool ext_xtheadmempair;
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bool ext_xtheadsync;
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bool ext_XVentanaCondOps;
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uint32_t pmu_mask;
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char *priv_spec;
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char *user_spec;
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char *bext_spec;
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char *vext_spec;
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uint16_t vlen;
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uint16_t elen;
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uint16_t cbom_blocksize;
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uint16_t cbop_blocksize;
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uint16_t cboz_blocksize;
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bool mmu;
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bool pmp;
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bool debug;
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bool misa_w;
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bool short_isa_string;
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#ifndef CONFIG_USER_ONLY
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RISCVSATPMap satp_mode;
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#endif
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};
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typedef struct RISCVCPUConfig RISCVCPUConfig;
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/* Helper functions to test for extensions. */
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static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unused__)))
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{
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return true;
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}
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static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
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{
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return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
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cfg->ext_xtheadbs || cfg->ext_xtheadcmo ||
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cfg->ext_xtheadcondmov ||
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cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv ||
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cfg->ext_xtheadmac || cfg->ext_xtheadmemidx ||
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cfg->ext_xtheadmempair || cfg->ext_xtheadsync;
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}
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#define MATERIALISE_EXT_PREDICATE(ext) \
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static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \
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{ \
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return cfg->ext_ ## ext ; \
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}
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MATERIALISE_EXT_PREDICATE(xtheadba)
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MATERIALISE_EXT_PREDICATE(xtheadbb)
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MATERIALISE_EXT_PREDICATE(xtheadbs)
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MATERIALISE_EXT_PREDICATE(xtheadcmo)
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MATERIALISE_EXT_PREDICATE(xtheadcondmov)
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MATERIALISE_EXT_PREDICATE(xtheadfmemidx)
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MATERIALISE_EXT_PREDICATE(xtheadfmv)
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MATERIALISE_EXT_PREDICATE(xtheadmac)
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MATERIALISE_EXT_PREDICATE(xtheadmemidx)
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MATERIALISE_EXT_PREDICATE(xtheadmempair)
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MATERIALISE_EXT_PREDICATE(xtheadsync)
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MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
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#endif
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