c9ba79baca
* hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing * hw/intc/arm_gic: Fix deactivation of SPI lines * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu * hw/misc: Set valid access size for Exynos4210 RNG * hw/arm/sbsa-ref: switch to 1GHz timer frequency * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine * hw/arm/virt: allow creation of a second NonSecure UART * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs * scripts/coverity-scan/COMPONENTS.md: update component regexes * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1 -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmZ2vigZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mRzD/9+Upo0E9GoNE8FaZYk+xw9 tB7V0C5RxZCW74ggjsoRSs2Mq45X+jzjT5cmlo3bCyj9z146eyOovcqroJHlggy7 W3nqE7Yg6tUz6MEbrDq54BVNGmBdwY4kpYr5MvXrhtb9A+/QjaW8MqlmT5NCvUb+ KZ+i4PTAF5dALCZblnqL5+9RYfwMOeR8R03ZbV2H0OCvO16N1rWsgoRzReVbpmy2 LEXGber13O7HnSRiMjvxTn92yZBO+tgmLB5w6V4aaYKEhj3B0wTO+GVEUMz0Rmzw LunrZhtQql9MOrdJIvgPrrFRmGHamnNu3IV0750xrRPQ1mJlVevaaCpl1IlaVeXG /PnY8HWaDJgwlPMDZVga38KSVQavdC8/Uvdw816a0rBzbclAAUZSNf8cuNeJ7qmk 2CQp/C8vuarWH0Ut0Qav8uuepd5jDt5TT3crBPhxMRwxsNTsSgjXxe7s3jdVWe2C +z1sC/KnSmmFUwyu14GA4WsUdz05m4Mmixz4unXemMeexibUA3n4RSTiUYzTNcb4 NmhEY4WbhuDtnSqqeSFyKtS5WCIG9A8YmcEzHWNsbaZAIEdS5QlxCSocbzG2mO6G zD/kWMn0nmYWejYgaT3LcL5BvkwmePV6u3jQNmVL8aQgG+OPZh7tvCR2gSMPWpml Y2pVvKZ+Tcx3GqZOUqKsrA== =oPnm -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240622' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue * hw/arm/xilinx_zynq: Fix IRQ/FIQ routing * hw/intc/arm_gic: Fix deactivation of SPI lines * hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu * hw/misc: Set valid access size for Exynos4210 RNG * hw/arm/sbsa-ref: switch to 1GHz timer frequency * hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine * hw/arm/virt: allow creation of a second NonSecure UART * hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs * scripts/coverity-scan/COMPONENTS.md: update component regexes * hw/usb/hcd-dwc2: Handle invalid address access in read and write functions * hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmZ2vigZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mRzD/9+Upo0E9GoNE8FaZYk+xw9 # tB7V0C5RxZCW74ggjsoRSs2Mq45X+jzjT5cmlo3bCyj9z146eyOovcqroJHlggy7 # W3nqE7Yg6tUz6MEbrDq54BVNGmBdwY4kpYr5MvXrhtb9A+/QjaW8MqlmT5NCvUb+ # KZ+i4PTAF5dALCZblnqL5+9RYfwMOeR8R03ZbV2H0OCvO16N1rWsgoRzReVbpmy2 # LEXGber13O7HnSRiMjvxTn92yZBO+tgmLB5w6V4aaYKEhj3B0wTO+GVEUMz0Rmzw # LunrZhtQql9MOrdJIvgPrrFRmGHamnNu3IV0750xrRPQ1mJlVevaaCpl1IlaVeXG # /PnY8HWaDJgwlPMDZVga38KSVQavdC8/Uvdw816a0rBzbclAAUZSNf8cuNeJ7qmk # 2CQp/C8vuarWH0Ut0Qav8uuepd5jDt5TT3crBPhxMRwxsNTsSgjXxe7s3jdVWe2C # +z1sC/KnSmmFUwyu14GA4WsUdz05m4Mmixz4unXemMeexibUA3n4RSTiUYzTNcb4 # NmhEY4WbhuDtnSqqeSFyKtS5WCIG9A8YmcEzHWNsbaZAIEdS5QlxCSocbzG2mO6G # zD/kWMn0nmYWejYgaT3LcL5BvkwmePV6u3jQNmVL8aQgG+OPZh7tvCR2gSMPWpml # Y2pVvKZ+Tcx3GqZOUqKsrA== # =oPnm # -----END PGP SIGNATURE----- # gpg: Signature made Sat 22 Jun 2024 05:06:00 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240622' of https://git.linaro.org/people/pmaydell/qemu-arm: hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine hw/usb/hcd-ohci: Fix ohci_service_td: accept zero-length TDs where CBP=BE+1 hw/misc: Set valid access size for Exynos4210 RNG hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUs hw/arm/virt: allow creation of a second NonSecure UART hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01] hw/arm/virt: Add serial aliases in DTB hw/usb/hcd-dwc2: Handle invalid address access in read and write functions hw/timer/a9gtimer: Handle QTest mode in a9_gtimer_get_current_cpu scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibs scripts/coverity-scan/COMPONENTS.md: Fix monitor component scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to the crypto component scripts/coverity-scan/COMPONENTS.md: Fix 'char' component scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CI hw/arm/xilinx_zynq: Fix IRQ/FIQ routing hw/intc/arm_gic: Fix deactivation of SPI lines hw/arm/sbsa-ref: switch to 1GHz timer frequency hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queue Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
||
---|---|---|
.. | ||
_templates | ||
about | ||
config | ||
devel | ||
interop | ||
specs | ||
sphinx | ||
sphinx-static | ||
spin | ||
system | ||
tools | ||
user | ||
block-replication.txt | ||
bypass-iommu.txt | ||
COLO-FT.txt | ||
colo-proxy.txt | ||
conf.py | ||
defs.rst.inc | ||
igd-assign.txt | ||
image-fuzzer.txt | ||
index.rst | ||
memory-hotplug.txt | ||
meson.build | ||
multi-thread-compression.txt | ||
multiseat.txt | ||
nvdimm.txt | ||
pci_expander_bridge.txt | ||
pcie_pci_bridge.txt | ||
pcie_sriov.txt | ||
pcie.txt | ||
qcow2-cache.txt | ||
qdev-device-use.txt | ||
qemu-option-trace.rst.inc | ||
qemupciserial.inf | ||
rdma.txt | ||
requirements.txt | ||
spice-port-fqdn.txt | ||
throttle.txt | ||
xbzrle.txt | ||
xen-save-devices-state.txt |