198c0d1f9d
According to the PoP channel command words (CCW) must be doubleword aligned and 31 bit addressable for format 1 and 24 bit addressable for format 0 CCWs. If the channel subsystem encounters a ccw address which does not satisfy this alignment requirement a program-check condition is recognised. The situation with 31 bit addressable is a bit more complicated: both the ORB and a format 1 CCW TIC hold the address of (the rest of) the channel program, that is the address of the next CCW in a word, and the PoP mandates that bit 0 of that word shall be zero -- or a program-check condition is to be recognized -- and does not belong to the field holding the ccw address. Since in code the corresponding fields span across the whole word (unlike in PoP where these are defined as 31 bit wide) we can check this by applying a mask. The 24 addressable case isn't affecting TIC because the address is composed of a halfword and a byte portion (no additional zero bit requirements) and just slightly complicates the ORB case where also bits 1-7 need to be zero. The same requirements (especially n-bit addressability) apply to the ccw addresses generated while chaining. Let's make our CSS implementation follow the AR more closely. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20170727154842.23427-1-pasic@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> |
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3270-ccw.c | ||
ccw-device.c | ||
ccw-device.h | ||
css-bridge.c | ||
css.c | ||
event-facility.c | ||
ipl.c | ||
ipl.h | ||
Makefile.objs | ||
s390-ccw.c | ||
s390-pci-bus.c | ||
s390-pci-bus.h | ||
s390-pci-inst.c | ||
s390-pci-inst.h | ||
s390-skeys-kvm.c | ||
s390-skeys.c | ||
s390-stattrib-kvm.c | ||
s390-stattrib.c | ||
s390-virtio-ccw.c | ||
s390-virtio-hcall.c | ||
s390-virtio.c | ||
s390-virtio.h | ||
sclp.c | ||
sclpcpu.c | ||
sclpquiesce.c | ||
trace-events | ||
virtio-ccw.c | ||
virtio-ccw.h |