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193eb522e4
qemu/target/riscv/insn_trans
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Weiwei Li 193eb522e4 target/riscv: add support for Zcmp extension 
Add encode, trans* functions for Zcmp instructions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05 10:49:50 +10:00
..
trans_privileged.c.inc target/riscv: Add itrigger support when icount is not enabled 2023-01-06 10:42:55 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvd.c.inc target/riscv: add support for Zcd extension 2023-05-05 10:49:50 +10:00
trans_rvf.c.inc target/riscv: add support for Zcf extension 2023-05-05 10:49:50 +10:00
trans_rvh.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvi.c.inc target/riscv: add support for Zca extension 2023-05-05 10:49:50 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvv.c.inc target/riscv: Avoid tcg_const_* 2023-03-05 13:46:13 -08:00
trans_rvzawrs.c.inc RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
trans_rvzce.c.inc target/riscv: add support for Zcmp extension 2023-05-05 10:49:50 +10:00
trans_rvzfh.c.inc target/riscv: Avoid tcg_const_* 2023-03-05 13:46:13 -08:00
trans_rvzicbo.c.inc target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xthead.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00