db7dfd4c7e
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/*
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* Allwinner A10 SoC emulation
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*
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* Copyright (C) 2013 Li Guang
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* Written by Li Guang <lig.fnst@cn.fujitsu.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "hw/sysbus.h"
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#include "hw/devices.h"
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#include "hw/arm/allwinner-a10.h"
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static void aw_a10_init(Object *obj)
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{
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AwA10State *s = AW_A10(obj);
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object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU);
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object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
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object_initialize(&s->intc, sizeof(s->intc), TYPE_AW_A10_PIC);
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qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
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object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT);
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qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
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object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
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qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
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if (nd_table[0].used) {
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qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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}
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static void aw_a10_realize(DeviceState *dev, Error **errp)
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{
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AwA10State *s = AW_A10(dev);
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SysBusDevice *sysbusdev;
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uint8_t i;
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qemu_irq fiq, irq;
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Error *err = NULL;
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object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
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fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
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object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->intc);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
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sysbus_connect_irq(sysbusdev, 0, irq);
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sysbus_connect_irq(sysbusdev, 1, fiq);
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for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
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s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
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}
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object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->timer);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
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sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
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sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
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sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
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sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
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sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
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sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
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object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbusdev = SYS_BUS_DEVICE(&s->emac);
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sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
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sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
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serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
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115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
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}
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static void aw_a10_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = aw_a10_realize;
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}
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static const TypeInfo aw_a10_type_info = {
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.name = TYPE_AW_A10,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(AwA10State),
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.instance_init = aw_a10_init,
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.class_init = aw_a10_class_init,
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};
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static void aw_a10_register_types(void)
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{
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type_register_static(&aw_a10_type_info);
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}
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type_init(aw_a10_register_types)
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